50 lines
1.1 KiB
Systemverilog
50 lines
1.1 KiB
Systemverilog
/**
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* VFPGA TOP
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*
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* Tie up all signals to the user kernels
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* Still to this day, interfaces are not supported by Vivado packager ...
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* This means verilog style port connections are needed.
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*
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*/
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import lynxTypes::*;
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// Instantiate top level
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`ifdef EN_STRM
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perf_local inst_host_link (
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.axis_sink (axis_host_recv[0]),
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.axis_src (axis_host_send[0]),
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.aclk (aclk),
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.aresetn (aresetn)
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);
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`endif
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`ifdef EN_MEM
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perf_local inst_card_link (
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.axis_sink (axis_card_recv[0]),
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.axis_src (axis_card_send[0]),
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.aclk (aclk),
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.aresetn (aresetn)
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);
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`endif
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// Tie-off unused
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always_comb axi_ctrl.tie_off_s();
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always_comb notify.tie_off_m();
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always_comb sq_rd.tie_off_m();
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always_comb sq_wr.tie_off_m();
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always_comb cq_rd.tie_off_s();
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always_comb cq_wr.tie_off_s();
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// ILA
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ila_perf_host inst_ila_perf_host (
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.clk(aclk),
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.probe0(axis_host_recv[0].tvalid),
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.probe1(axis_host_recv[0].tready),
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.probe2(axis_host_recv[0].tlast),
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.probe3(axis_card_recv[0].tvalid),
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.probe4(axis_card_recv[0].tready),
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.probe5(axis_card_recv[0].tlast)
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); |