243 lines
7.8 KiB
Systemverilog
243 lines
7.8 KiB
Systemverilog
always_comb notify.tie_off_m();
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// I/O
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AXI4SR axis_sink_int[N_STRM_AXI]();
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AXI4SR axis_src_int[N_STRM_AXI]();
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`ifndef EN_MEM
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for (genvar i = 0; i < N_STRM_AXI; i++) begin
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axisr_reg inst_reg_sink_0 (.aclk(aclk), .aresetn(aresetn), .s_axis(axis_host_recv[i]), .m_axis(axis_sink_int[i]));
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axisr_reg inst_reg_src_0 (.aclk(aclk), .aresetn(aresetn), .s_axis(axis_src_int[i]), .m_axis(axis_host_send[i]));
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end
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`else
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for (genvar i = 0; i < N_CARD_AXI; i++) begin
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axisr_reg inst_reg_sink_0 (.aclk(aclk), .aresetn(aresetn), .s_axis(axis_card_recv[i]), .m_axis(axis_sink_int[i]));
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axisr_reg inst_reg_src_0 (.aclk(aclk), .aresetn(aresetn), .s_axis(axis_src_int[i]), .m_axis(axis_card_send[i]));
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end
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`endif
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// UL
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parameter integer START_RD = 0;
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parameter integer START_WR = 1;
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// Benchmark slave
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logic [1:0] bench_ctrl;
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logic [31:0] bench_done;
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logic [63:0] bench_timer;
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logic [PID_BITS-1:0] bench_pid;
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logic [DEST_BITS-1:0] bench_dest;
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logic [VADDR_BITS-1:0] bench_vaddr;
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logic [LEN_BITS-1:0] bench_len;
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logic [31:0] bench_n_reps;
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logic [63:0] bench_n_beats;
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logic done_req;
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logic done_data;
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logic [63:0] cnt_data;
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logic [31:0] bench_sent;
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typedef enum logic[1:0] {ST_IDLE, ST_READ, ST_WRITE} state_t;
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logic [1:0] state_C;
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logic[15:0] cnt_cq_rd;
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logic[15:0] cnt_cq_wr;
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always_ff @(posedge aclk) begin
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if(~aresetn) begin
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cnt_cq_rd <= 0;
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cnt_cq_wr <= 0;
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end
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else begin
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cnt_cq_rd <= cq_rd.valid ? cnt_cq_rd + 1 : cnt_cq_rd;
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cnt_cq_wr <= cq_wr.valid ? cnt_cq_wr + 1 : cnt_cq_wr;
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end
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end
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//
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// CSR
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//
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perf_fpga_slv inst_slave (
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.aclk(aclk),
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.aresetn(aresetn),
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.axi_ctrl(axi_ctrl),
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.bench_ctrl(bench_ctrl),
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.bench_done(bench_done),
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.bench_timer(bench_timer),
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.bench_pid(bench_pid),
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.bench_dest(bench_dest),
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.bench_vaddr(bench_vaddr),
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.bench_len(bench_len),
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.bench_n_reps(bench_n_reps),
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.bench_n_beats(bench_n_beats)
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);
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AXI4SR axis_sink_active ();
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AXI4SR axis_src_active ();
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// active interface according to bench dest
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// sink
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assign axis_sink_active.tvalid = (bench_dest == 0) ? axis_sink_int[0].tvalid : axis_sink_int[1].tvalid;
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assign axis_sink_active.tkeep = (bench_dest == 0) ? axis_sink_int[0].tkeep : axis_sink_int[1].tkeep;
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assign axis_sink_active.tlast = (bench_dest == 0) ? axis_sink_int[0].tlast : axis_sink_int[1].tlast;
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assign axis_sink_active.tdata = (bench_dest == 0) ? axis_sink_int[0].tdata : axis_sink_int[1].tdata;
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assign axis_sink_active.tid = (bench_dest == 0) ? axis_sink_int[0].tid : axis_sink_int[1].tid;
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assign axis_sink_int[0].tready = (bench_dest == 0) ? axis_sink_active.tready : 1'b0;
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assign axis_sink_int[1].tready = (bench_dest == 0) ? 1'b0 : axis_sink_active.tready;
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// src
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assign axis_src_int[0].tvalid = (bench_dest == 0) ? axis_src_active.tvalid : 1'b0;
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assign axis_src_int[0].tkeep = axis_src_active.tkeep;
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assign axis_src_int[0].tlast = axis_src_active.tlast;
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assign axis_src_int[0].tdata = axis_src_active.tdata;
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assign axis_src_int[0].tid = axis_src_active.tid;
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assign axis_src_int[1].tvalid = (bench_dest == 0) ? 1'b0 : axis_src_active.tvalid;
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assign axis_src_int[1].tkeep = axis_src_active.tkeep;
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assign axis_src_int[1].tlast = axis_src_active.tlast;
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assign axis_src_int[1].tdata = axis_src_active.tdata;
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assign axis_src_int[1].tid = axis_src_active.tid;
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assign axis_src_active.tready = (bench_dest == 0) ? axis_src_int[0].tready : axis_src_int[1].tready;
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// REG
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always_ff @(posedge aclk) begin
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if(aresetn == 1'b0) begin
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state_C <= ST_IDLE;
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bench_sent <= 'X;
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bench_done <= 'X;
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bench_timer <= 'X;
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done_req <= 'X;
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done_data <= 'X;
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cnt_data <= 'X;
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end else begin
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case(state_C)
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ST_IDLE: begin
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state_C <= bench_ctrl[START_RD] ? ST_READ :
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bench_ctrl[START_WR] ? ST_WRITE : ST_IDLE;
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bench_sent <= 0;
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done_req <= 1'b0;
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done_data <= 1'b0;
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cnt_data <= 0;
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end
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ST_READ: begin
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// Requests
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done_req <= ((bench_sent == bench_n_reps -1) && sq_rd.ready) ? 1'b1 : done_req;
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bench_sent <= (sq_rd.valid && sq_rd.ready) ? bench_sent + 1 : bench_sent;
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// Data
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done_data <= ((cnt_data == bench_n_beats - 1) && axis_sink_active.tvalid) ? 1'b1 : done_data;
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cnt_data <= (axis_sink_active.tvalid && axis_sink_active.tready) ? cnt_data + 1 : cnt_data;
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state_C <= (done_req && done_data) ? ST_IDLE : ST_READ;
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end
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ST_WRITE: begin
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// Requests
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done_req <= ((bench_sent == bench_n_reps -1) && sq_wr.ready) ? 1'b1 : done_req;
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bench_sent <= (sq_wr.valid && sq_wr.ready) ? bench_sent + 1 : bench_sent;
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// Data
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done_data <= ((cnt_data == bench_n_beats - 1) && axis_src_active.tready) ? 1'b1 : done_data;
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cnt_data <= (axis_src_active.tvalid && axis_src_active.tready) ? cnt_data + 1 : cnt_data;
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state_C <= (done_req && done_data) ? ST_IDLE : ST_WRITE;
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end
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endcase
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// Status
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bench_done <= (bench_ctrl[START_RD] || bench_ctrl[START_WR]) ? 0 :
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(cq_rd.valid || cq_wr.valid) ? bench_done + 1 : bench_done;
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bench_timer <= (bench_ctrl[START_RD] || bench_ctrl[START_WR]) ? 0 :
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(bench_done >= bench_n_reps) ? bench_timer : bench_timer + 1;
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end
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end
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// DP
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always_comb begin
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// Requests
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sq_rd.data = 0;
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sq_rd.data.opcode = LOCAL_READ;
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sq_rd.data.strm = STRM_HOST;
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sq_rd.data.mode = 0;
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sq_rd.data.rdma = 0;
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sq_rd.data.remote = 0;
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sq_rd.data.pid = bench_pid;
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sq_rd.data.dest = bench_dest;
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sq_rd.data.last = 1'b1;
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sq_rd.data.vaddr = bench_vaddr;
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sq_rd.data.len = bench_len;
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sq_rd.valid = (state_C == ST_READ) && ~done_req;
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sq_wr.data = 0;
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sq_wr.data.opcode = LOCAL_WRITE;
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sq_wr.data.strm = STRM_HOST;
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sq_wr.data.mode = 0;
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sq_wr.data.rdma = 0;
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sq_wr.data.remote = 0;
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sq_wr.data.pid = bench_pid;
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sq_wr.data.dest = bench_dest;
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sq_wr.data.last = 1'b1;
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sq_wr.data.vaddr = bench_vaddr;
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sq_wr.data.len = bench_len;
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sq_wr.valid = (state_C == ST_WRITE) && ~done_req;
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cq_rd.ready = 1'b1;
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cq_wr.ready = 1'b1;
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// Data
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axis_sink_active.tready = (state_C == ST_READ) && ~done_data;
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axis_src_active.tdata = cnt_data + 1;
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axis_src_active.tkeep = ~0;
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axis_src_active.tid = 0;
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axis_src_active.tlast = 1'b0;
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axis_src_active.tvalid = (state_C == ST_WRITE) && ~done_data;
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end
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// Debug
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ila_perf_fpga inst_ila_perf_fpga (
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.clk(aclk),
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.probe0(bench_ctrl), // 2
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.probe1(bench_done), // 32
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.probe2(bench_timer), // 64
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.probe3(bench_vaddr), // 48
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.probe4(bench_len), // 28
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.probe5(bench_pid), // 6
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.probe6(bench_n_reps), // 32
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.probe7(bench_n_beats), // 64
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.probe8(done_req),
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.probe9(done_data),
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.probe10(cnt_data), // 64
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.probe11(bench_sent), // 32
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.probe12(cnt_cq_rd), // 16
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.probe13(cnt_cq_wr), // 16
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.probe14(axis_sink_int[0].tvalid),
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.probe15(axis_sink_int[0].tready),
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.probe16(axis_sink_int[0].tlast),
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.probe17(axis_src_int[0].tvalid),
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.probe18(axis_src_int[0].tready),
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.probe19(axis_src_int[0].tlast),
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.probe20(axis_sink_int[1].tvalid),
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.probe21(axis_sink_int[1].tready),
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.probe22(axis_sink_int[1].tlast),
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.probe23(axis_src_int[1].tvalid),
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.probe24(axis_src_int[1].tready),
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.probe25(axis_src_int[1].tlast),
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.probe26(cq_rd.valid),
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.probe27(cq_rd.data.pid), // 6
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.probe28(cq_rd.data.host),
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.probe29(cq_rd.data.dest), // 4
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.probe30(cq_wr.valid),
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.probe31(cq_wr.data.pid), // 6
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.probe32(cq_wr.data.host),
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.probe33(cq_wr.data.dest), // 4
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.probe34(bench_dest), // 4
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.probe35(sq_wr.valid),
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.probe36(sq_rd.valid)
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);
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