150 lines
5.4 KiB
Systemverilog
150 lines
5.4 KiB
Systemverilog
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/*
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* Copyright 2019 - 2020 Systems Group, ETH Zurich
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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module quick_fifo #(
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parameter FIFO_WIDTH = 32,
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parameter FIFO_DEPTH_BITS = 8,
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parameter FIFO_ALMOSTFULL_THRESHOLD = 2**FIFO_DEPTH_BITS - 4
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) (
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input wire clk,
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input wire reset_n,
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input wire we, // input write enable
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input wire [FIFO_WIDTH - 1:0] din, // input write data with configurable width
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input wire re, // input read enable
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output reg valid, // dout valid
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output reg [FIFO_WIDTH - 1:0] dout, // output read data with configurable width
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output reg [FIFO_DEPTH_BITS - 1:0] count, // output FIFOcount
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output reg empty, // output FIFO empty
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output reg full, // output FIFO full
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output reg almostfull // output configurable programmable full/ almost full
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);
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reg [FIFO_DEPTH_BITS - 1:0] rp = 0;
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reg [FIFO_DEPTH_BITS - 1:0] wp = 0;
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reg [FIFO_DEPTH_BITS - 1:0] mem_count = 0; // output FIFOcount
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reg mem_empty = 1'b1;
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reg valid_t1 = 0, valid_t2 = 0;
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reg valid0 = 0;
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wire remem;
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wire wemem;
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wire remem_valid;
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wire [FIFO_WIDTH-1:0] dout_mem;
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assign remem = (re & valid_t1 & valid_t2) | ~(valid_t1 & valid_t2);
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assign wemem = we & ~full;
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assign remem_valid = remem & ~mem_empty;
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bram #(.DATA_WIDTH(FIFO_WIDTH),
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.ADDR_WIDTH(FIFO_DEPTH_BITS)) fifo_mem(
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.clk (clk),
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.we (wemem),
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.re (remem),
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.raddr (rp),
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.waddr (wp),
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.din (din),
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.dout (dout_mem)
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);
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// data
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always @(posedge clk) begin
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dout <= (valid_t2)? ((re)? dout_mem : dout) : dout_mem;
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end
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// valids, flags
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always @(posedge clk) begin
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if (~reset_n) begin
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empty <= 1'b1;
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full <= 1'b0;
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almostfull <= 1'b0;
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count <= 0; //32'b0;
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rp <= 0;
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wp <= 0;
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valid_t2 <= 1'b0;
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valid_t1 <= 1'b0;
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mem_empty <= 1'b1;
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mem_count <= 'b0;
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//dout <= 0;
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valid <= 0;
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valid0 <= 0;
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end
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else begin
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valid <= (valid)? ((re)? valid0 : 1'b1) : valid0;
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valid0 <= (remem)? ~mem_empty : valid0;
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valid_t2 <= (valid_t2)? ((re)? valid_t1 : 1'b1) : valid_t1;
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valid_t1 <= (remem)? ~mem_empty : valid_t1;
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rp <= (remem & ~mem_empty)? (rp + 1'b1) : rp;
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wp <= (wemem)? (wp + 1'b1) : wp;
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// mem_empty
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if (we) mem_empty <= 1'b0;
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else if(remem & (mem_count == 1'b1)) mem_empty <= 1'b1;
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// mem_count
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if( wemem & ~remem_valid) mem_count <= mem_count + 1'b1;
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else if (~wemem & remem_valid) mem_count <= mem_count - 1'b1;
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// empty
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if (we) empty <= 1'b0;
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else if((re & valid_t2 & ~valid_t1) & (count == 1'b1)) empty <= 1'b1;
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// count
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if( wemem & (~(re & valid_t2) | ~re) ) count <= count + 1'b1;
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else if (~wemem & (re & valid_t2)) count <= count - 1'b1;
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//
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if (we & ~re) begin
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if (count == (2**FIFO_DEPTH_BITS-1))
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full <= 1'b1;
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if (count == (FIFO_ALMOSTFULL_THRESHOLD-1))
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almostfull <= 1'b1;
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end
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//
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if ((~we | full) & re) begin //
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full <= 1'b0;
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if (count == FIFO_ALMOSTFULL_THRESHOLD)
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almostfull <= 1'b0;
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end
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end
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end
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endmodule
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