108 lines
4.6 KiB
Systemverilog
108 lines
4.6 KiB
Systemverilog
// Copyright (c) 2001-2018 Intel Corporation
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//
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// Permission is hereby granted, free of charge, to any person obtaining a
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// copy of this software and associated documentation files (the
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// "Software"), to deal in the Software without restriction, including
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// without limitation the rights to use, copy, modify, merge, publish,
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// distribute, sublicense, and/or sell copies of the Software, and to
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// permit persons to whom the Software is furnished to do so, subject to
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// the following conditions:
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//
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// The above copyright notice and this permission notice shall be included
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// in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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// OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
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// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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// synopsys translate_off
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`timescale 1 ps / 1 ps
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// synopsys translate_on
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module logic_dsp_unsigned_27x27_atom
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(
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input wire clk_i,
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input wire clr,
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input wire [26:0] ax,
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input wire [26:0] ay,
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input wire accu_en,
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output wire [53:0] resulta
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);
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wire [2:0] clk = {clk_i, clk_i, clk_i};
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wire [1:0] aclr = {clr, clr};
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wire [2:0] ena = 3'b111;
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twentynm_mac twentynm_mac_component
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(
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.aclr (aclr),
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.ax (ax),
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.ay (ay),
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.clk (clk),
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.ena (ena),
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.resulta(resulta),
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.accumulate(accu_en)
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);
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defparam
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twentynm_mac_component.ax_width = 27,
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twentynm_mac_component.ay_scan_in_width = 27,
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twentynm_mac_component.operation_mode = "m27x27",
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twentynm_mac_component.mode_sub_location = 0,
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twentynm_mac_component.operand_source_max = "input",
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twentynm_mac_component.operand_source_may = "input",
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twentynm_mac_component.operand_source_mbx = "input",
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twentynm_mac_component.operand_source_mby = "input",
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twentynm_mac_component.signed_max = "false",
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twentynm_mac_component.signed_may = "false",
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twentynm_mac_component.signed_mbx = "false",
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twentynm_mac_component.signed_mby = "false",
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twentynm_mac_component.preadder_subtract_a = "false",
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twentynm_mac_component.preadder_subtract_b = "false",
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twentynm_mac_component.ay_use_scan_in = "false",
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twentynm_mac_component.by_use_scan_in = "false",
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twentynm_mac_component.delay_scan_out_ay = "false",
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twentynm_mac_component.delay_scan_out_by = "false",
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twentynm_mac_component.use_chainadder = "false",
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twentynm_mac_component.enable_double_accum = "false",
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twentynm_mac_component.load_const_value = 0,
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twentynm_mac_component.coef_a_0 = 0,
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twentynm_mac_component.coef_a_1 = 0,
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twentynm_mac_component.coef_a_2 = 0,
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twentynm_mac_component.coef_a_3 = 0,
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twentynm_mac_component.coef_a_4 = 0,
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twentynm_mac_component.coef_a_5 = 0,
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twentynm_mac_component.coef_a_6 = 0,
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twentynm_mac_component.coef_a_7 = 0,
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twentynm_mac_component.coef_b_0 = 0,
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twentynm_mac_component.coef_b_1 = 0,
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twentynm_mac_component.coef_b_2 = 0,
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twentynm_mac_component.coef_b_3 = 0,
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twentynm_mac_component.coef_b_4 = 0,
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twentynm_mac_component.coef_b_5 = 0,
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twentynm_mac_component.coef_b_6 = 0,
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twentynm_mac_component.coef_b_7 = 0,
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twentynm_mac_component.ax_clock = "0",
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twentynm_mac_component.ay_scan_in_clock = "0",
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twentynm_mac_component.az_clock = "none",
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twentynm_mac_component.bx_clock = "none",
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twentynm_mac_component.by_clock = "none",
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twentynm_mac_component.bz_clock = "none",
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twentynm_mac_component.coef_sel_a_clock = "none",
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twentynm_mac_component.coef_sel_b_clock = "none",
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twentynm_mac_component.sub_clock = "none",
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twentynm_mac_component.sub_pipeline_clock = "none",
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twentynm_mac_component.negate_clock = "none",
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twentynm_mac_component.negate_pipeline_clock = "none",
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twentynm_mac_component.accumulate_clock = "none",
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twentynm_mac_component.accum_pipeline_clock = "none",
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twentynm_mac_component.load_const_clock = "none",
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twentynm_mac_component.load_const_pipeline_clock = "none",
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twentynm_mac_component.input_pipeline_clock = "none",
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twentynm_mac_component.output_clock = "0",
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twentynm_mac_component.scan_out_width = 18,
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twentynm_mac_component.result_a_width = 54;
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endmodule |