140 lines
3.6 KiB
Systemverilog
140 lines
3.6 KiB
Systemverilog
/*
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* Copyright 2019 - 2020 Systems Group, ETH Zurich
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*
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* This hardware operator is free software: you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as published
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* by the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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`default_nettype none
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import kmeansTypes::*;
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module k_means_division
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(
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input wire clk, // Clock
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input wire rst_n, // Asynchronous reset active low
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input wire start_operator,
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input wire [63:0] div_sum,
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input wire [63:0] div_count,
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input wire div_valid,
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input wire div_last_dim,
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input wire div_last,
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output wire div_dout_last_dim,
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output wire div_dout_last,
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output reg [MAX_DIM_WIDTH-1:0] div_dout, //the center data for updating the cluster in dist processors
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output wire div_dout_valid, //when high, means up_center_o valids, goes to div_dout stage in the higher hierarchy
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//debug counter
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output reg [31:0] k_means_division_debug_cnt
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);
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localparam LPM_WIDTHN = 40;
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localparam LPM_PIPELINE = 40;
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reg rst_delay_n;
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wire [LPM_WIDTHN-1:0] divider_quotient;
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logic [63:0] divider_denummer;
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//shift registers
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reg[LPM_PIPELINE:0] div_valid_sr;
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reg[LPM_PIPELINE:0] div_last_dim_sr;
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reg[LPM_PIPELINE:0] div_last_sr;
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always_ff @(posedge clk)begin
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rst_delay_n <= rst_n;
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end
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always_comb begin : proc_denumer
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if(div_valid && (div_count==0)) begin
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divider_denummer = 1;
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end
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else begin
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divider_denummer = div_count;
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end
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end
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/*
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lpm_divide #(
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.lpm_widthn(LPM_WIDTHN), // 40
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.lpm_widthd(32),
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.lpm_pipeline(LPM_PIPELINE), // 40
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.lpm_nrepresentation("UNSIGNED"),
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.lpm_drepresentation("UNSIGNED")
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// .LPM_NREPRESENTATION("unsigned"),
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// .LPM_DREPRESENTATION("unsigned")
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)
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divider
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(
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.clock(clk),
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.clken(1'b1),
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.aclr(1'b0),
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.quotient(divider_quotient),
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.numer(div_sum[LPM_WIDTHN-1:0]),
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.denom(divider_denummer[31:0]),
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.remain()
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);
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*/
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logic [71:0] tmp;
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div_gen_0 inst_div_gen (
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.aclk(clk),
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.s_axis_divisor_tvalid(1'b1),
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.s_axis_divisor_tdata(divider_denummer[31:0]),
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.s_axis_dividend_tvalid(1'b1),
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.s_axis_dividend_tdata(div_sum[LPM_WIDTHN-1:0]),
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.m_axis_dout_tvalid(),
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.m_axis_dout_tdata(tmp)
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);
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assign divider_quotient = tmp[32+:40];
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assign div_dout_valid = div_valid_sr[0];
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assign div_dout_last_dim = div_last_dim_sr[0];
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assign div_dout_last = div_last_sr[0];
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always @(posedge clk) begin
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div_dout <= divider_quotient[31:0];
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if (~rst_delay_n) begin
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div_valid_sr <= 0;
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div_last_dim_sr <= 0;
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div_last_sr <= 0;
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end
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else begin
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div_valid_sr <= {div_valid, div_valid_sr[LPM_PIPELINE:1]};
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div_last_dim_sr <= {div_last_dim, div_last_dim_sr[LPM_PIPELINE:1]};
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div_last_sr <= {div_last, div_last_sr[LPM_PIPELINE:1]};
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end
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end
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//debug counters
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reg [31:0] division_output_cnt;
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always @ (posedge clk) begin
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if(start_operator) begin
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division_output_cnt <= '0;
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end
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else if(div_dout_valid) begin
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division_output_cnt <= division_output_cnt + 1'b1;
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end
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k_means_division_debug_cnt <= division_output_cnt;
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end
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endmodule
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`default_nettype wire
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