69 lines
2.4 KiB
Systemverilog
69 lines
2.4 KiB
Systemverilog
// Copyright (c) 2013-2015, Intel Corporation
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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// * Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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// * Redistributions in binary form must reproduce the above copyright notice,
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// this list of conditions and the following disclaimer in the documentation
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// and/or other materials provided with the distribution.
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// * Neither the name of Intel Corporation nor the names of its contributors
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// may be used to endorse or promote products derived from this software
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// without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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// POSSIBILITY OF SUCH DAMAGE.
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module dual_port_ram #(
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parameter DATA_WIDTH = 32,
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parameter ADDR_WIDTH = 8
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)
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(
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input wire clk,
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input wire we,
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input wire re,
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input wire [ADDR_WIDTH-1:0] raddr,
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input wire [ADDR_WIDTH-1:0] waddr,
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input wire [DATA_WIDTH-1:0] din,
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output reg [DATA_WIDTH-1:0] dout
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);
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`ifdef VENDOR_XILINX
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(* ram_extract = "yes", ram_style = "block" *)
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reg [DATA_WIDTH-1:0] mem[0:2**ADDR_WIDTH-1];
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`else
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/*(* ramstyle = "no_rw_check" *)*/ reg [DATA_WIDTH-1:0] mem[0:2**ADDR_WIDTH-1];
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`endif
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initial
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begin
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for (int i = 0; i < 2**ADDR_WIDTH; i++) begin
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mem [i] = '0;
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end
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end
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always @(posedge clk) begin
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if (we)
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mem[waddr] <= din;
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if (re)
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dout <= mem[raddr];
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end
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endmodule |