106 lines
3.2 KiB
Systemverilog
106 lines
3.2 KiB
Systemverilog
/*
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* Copyright 2019 - 2020 Systems Group, ETH Zurich
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*
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* This hardware operator is free software: you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as published
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* by the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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import kmeansTypes::*;
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module dist_processor #(parameter INDEX_PROCESSOR = 0)
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(
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input wire clk, // Clock
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input wire rst_n, // Asynchronous reset active low
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input wire [5:0] numBits_minus_1,
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input wire [MAX_DEPTH_BITS:0] data_dim_minus_1,
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input wire enable,
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//----------- bit serial data---------------//
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input wire bs_data_valid_i,
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input wire [NUM_BANK-1:0] bs_data_i,
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//-----------input centroid----------------------//
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input wire [NUM_BANK-1:0][31:0] centroid_i,
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input wire [47:0] centroid_norm_half,
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//---------------previous processor assignment result---//
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input wire min_dist_valid_i,
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input wire signed [47:0] min_dist_i,
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input wire [NUM_CLUSTER_BITS:0] cluster_i,
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//--------------current processor assignment result--------//
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output wire min_dist_valid_o,
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output wire signed [47:0] min_dist_o,
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output wire [NUM_CLUSTER_BITS:0] cluster_o
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);
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//////////////////////////////input register//////////////////////////////////////////////
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reg rst_n_reg;
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reg enable_reg;
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always @(posedge clk ) begin
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rst_n_reg <= rst_n;
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enable_reg <= enable;
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end
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///////////////////Calculate distance///////////////////////////////
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wire signed [47:0] distance;
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wire dist_valid;
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bit_serial_mul_accu bit_serial_mul_accu
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(
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.clk (clk),
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.rst_n (rst_n_reg),
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.numBits_minus_1(numBits_minus_1),
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.data_dim_minus_1(data_dim_minus_1),
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.x_norm_half (centroid_norm_half),
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.x (centroid_i),
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.a_valid (bs_data_valid_i),
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.a (bs_data_i),
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.result (distance),
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.result_valid (dist_valid)
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);
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////////////////////////min dist selection/////////////////////////////
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reg min_dist_valid_reg;
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reg signed [47:0] min_dist_reg;
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reg [NUM_CLUSTER_BITS:0] cluster_reg;
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always @ (posedge clk) begin
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if(~rst_n_reg) begin
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min_dist_valid_reg <= 1'b0;
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end
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else begin
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min_dist_reg <= '0;
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cluster_reg <= '0;
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min_dist_valid_reg <= dist_valid;
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if(dist_valid & min_dist_valid_i) begin //dist valid and min dist valid should be set at the same cycle
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min_dist_reg <= ((distance<=min_dist_i) & enable_reg) ? distance : min_dist_i;
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cluster_reg <= ((distance<=min_dist_i) & enable_reg) ? INDEX_PROCESSOR : cluster_i;
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end
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end
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end
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assign min_dist_valid_o = min_dist_valid_reg;
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assign min_dist_o = min_dist_reg;
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assign cluster_o = cluster_reg;
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endmodule
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