141 lines
3.9 KiB
Systemverilog
141 lines
3.9 KiB
Systemverilog
/*
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* Copyright 2019 - 2020 Systems Group, ETH Zurich
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*
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* This hardware operator is free software: you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as published
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* by the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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`default_nettype none
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import kmeansTypes::*;
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module agg_div
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(
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input wire clk, // Clock
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input wire rst_n, // Asynchronous reset active low
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input wire start_operator,
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input wire [MAX_DEPTH_BITS:0] data_dim, //input the actual dimension of the data
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input wire [NUM_CLUSTER_BITS:0] num_cluster, //input the actual number of cluster
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input wire [63:0] agg_data,
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input wire agg_valid,
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output wire [MAX_DIM_WIDTH-1:0] update,
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output wire update_valid,
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output wire update_last,
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output wire update_last_dim,
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//debug counter
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output reg [7:0][31:0] agg_div_debug_cnt
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);
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wire [63:0] div_sum;
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wire [63:0] div_count;
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wire div_valid;
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wire div_last_dim;
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wire div_last;
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wire [63:0] sse;
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wire sse_valid;
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wire sse_converge;
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wire div_dout_last_dim;
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wire div_dout_last;
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wire [MAX_DIM_WIDTH-1:0] div_dout;
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wire div_dout_valid;
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reg [MAX_DEPTH_BITS:0] data_dim_reg;
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reg [NUM_CLUSTER_BITS:0] num_cluster_reg;
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wire [7:0] [31:0] k_means_aggregation_debug_cnt;
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wire [31:0] k_means_division_debug_cnt;
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reg rst_n_reg;
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reg start_operator_reg;
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always @ (posedge clk) begin
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rst_n_reg <= rst_n;
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start_operator_reg <= start_operator;
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end
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k_means_aggregation agg (
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.clk (clk),
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.rst_n (rst_n_reg),
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.start_operator (start_operator_reg),
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.data_dim (data_dim_reg),
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.num_cluster (num_cluster_reg),
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.agg_data (agg_data),
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.agg_valid (agg_valid),
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.div_sum (div_sum),
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.div_count (div_count),
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.div_valid (div_valid),
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.div_last_dim(div_last_dim),
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.div_last (div_last),
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.sse (sse),
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.sse_valid (sse_valid),
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.sse_converge(sse_converge),
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.k_means_aggregation_debug_cnt(k_means_aggregation_debug_cnt)
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);
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k_means_division division
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(
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.clk (clk),
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.rst_n (rst_n_reg),
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.start_operator (start_operator_reg),
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.div_sum (div_sum),
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.div_count (div_count),
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.div_valid (div_valid),
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.div_last_dim (div_last_dim),
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.div_last (div_last),
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.div_dout_last_dim(div_dout_last_dim),
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.div_dout_last (div_dout_last),
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.div_dout (div_dout),
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.div_dout_valid (div_dout_valid),
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.k_means_division_debug_cnt(k_means_division_debug_cnt)
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);
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div_buffer div_buffer(
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.clk (clk),
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.rst_n (rst_n_reg),
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.div_dout (div_dout),
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.div_dout_valid (div_dout_valid),
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.div_dout_last_dim(div_dout_last_dim),
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.div_dout_last (div_dout_last),
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.update (update),
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.update_valid (update_valid),
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.update_last (update_last),
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.update_last_dim (update_last_dim)
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);
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always @ (posedge clk) begin
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if(~rst_n_reg) begin
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num_cluster_reg <= '0;
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data_dim_reg <= '0;
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end
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else begin
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num_cluster_reg <= num_cluster;
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data_dim_reg <= data_dim;
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end
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agg_div_debug_cnt <= k_means_aggregation_debug_cnt;
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end
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endmodule
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`default_nettype wire
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