103 lines
3.7 KiB
Systemverilog
103 lines
3.7 KiB
Systemverilog
/*
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* Copyright 2017 - 2018, Zeke Wang, Systems Group, ETH Zurich
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*
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* This hardware operator is free software: you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as published
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* by the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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import kmeansTypes::*;
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module kmeans_adder_tree #(
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parameter TREE_DEPTH = NUM_PIPELINE_BITS,
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parameter TREE_WIDTH = 2**TREE_DEPTH
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)(
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input wire clk,
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input wire rst_n,
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//--------------------------Begin/Stop-----------------------------//
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//---------------------Input: External Memory rd response-----------------//
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input wire [TREE_WIDTH-1:0] [63:0] v_input, //
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input wire v_input_valid, //
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//------------------Output: disptach resp data to b of each bank---------------//
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output wire [63:0] v_output,
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output wire v_output_valid
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);
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reg rst_n_reg;
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always @ (posedge clk) begin
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rst_n_reg <= rst_n;
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end
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reg [63:0] v_intermdiate_result[TREE_DEPTH-1:0][TREE_WIDTH-1:0];
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reg v_intermdiate_result_valid[TREE_DEPTH-1:0];
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reg [63:0] v_intermdiate_result_reg[TREE_DEPTH-1:0][TREE_WIDTH-1:0];
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reg v_intermdiate_result_valid_reg[TREE_DEPTH-1:0];
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genvar d, w, b;
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generate
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for( d = 0; d < TREE_DEPTH; d = d + 1) begin: inst_adder_tree_depth
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for( w = 0; w < ( TREE_WIDTH/(2**(d+1)) ); w = w + 1) begin: inst_adder_tree_width
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always @(posedge clk) begin
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if(d == 0) begin
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v_intermdiate_result_reg[d][w] <= v_input[2*w] + v_input[2*w+1];
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v_intermdiate_result[d][w] <= v_intermdiate_result_reg[d][w];
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end
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else if(d > 0) begin
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v_intermdiate_result_reg[d][w] <= v_intermdiate_result[d-1][2*w] + v_intermdiate_result[d-1][2*w+1];
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v_intermdiate_result [d][w] <= v_intermdiate_result_reg[d][w];
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end
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else begin
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v_intermdiate_result[d][w] <= v_intermdiate_result[d-1][2*w] + v_intermdiate_result[d-1][2*w+1];
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end
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end
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end
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end
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endgenerate
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generate
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for( d = 0; d < TREE_DEPTH; d = d + 1) begin: inst_adder_tree_valid
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always @(posedge clk)
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begin
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if(~rst_n_reg)
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v_intermdiate_result_valid[d] <= 1'b0;
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else
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begin
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if(d == 0) begin
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v_intermdiate_result_valid_reg[d] <= v_input_valid;
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v_intermdiate_result_valid[d] <= v_intermdiate_result_valid_reg[d];
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end
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else if(d > 0) begin
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v_intermdiate_result_valid_reg[d] <= v_intermdiate_result_valid[d-1];
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v_intermdiate_result_valid[d] <= v_intermdiate_result_valid_reg[d] ;
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end
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else begin
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v_intermdiate_result_valid[d] <= v_intermdiate_result_valid[d-1];
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end
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end
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end
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end
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endgenerate
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assign v_output = v_intermdiate_result[TREE_DEPTH-1][0];
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assign v_output_valid = v_intermdiate_result_valid[TREE_DEPTH-1];
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endmodule |