124 lines
3.7 KiB
Systemverilog
124 lines
3.7 KiB
Systemverilog
/*
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* Copyright 2019 - 2020 Systems Group, ETH Zurich
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*
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* This hardware operator is free software: you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as published
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* by the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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import kmeansTypes::*;
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module Formatter (
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input wire clk, // Clock
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input wire rst_n, // Asynchronous reset active low
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input wire [NUM_CLUSTER_BITS:0] num_cluster,// the actual number of cluster that will be used
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input wire [MAX_DEPTH_BITS:0] data_dim, //input the actual dimension of the data
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input wire [7:0] precision,
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//interface to fetch engine
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input wire [511:0] tuple_cl,
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input wire tuple_cl_valid,
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input wire [511:0] centroid_cl, //not in bit-weaving format
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input wire centroid_cl_valid,
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output wire centroid_cl_ready,
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//interface to pipeline
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output wire [NUM_BANK*32-1:0] centroid_chunk,
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output wire centroid_chunk_valid,
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output wire last_chunk_of_all_centroid,
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output wire last_chunk_of_one_centroid,
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//interface to pipelines
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output reg [NUM_PIPELINE-1:0][NUM_BANK-1:0] tuple_bit,
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output reg tuple_bit_valid,
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output reg last_bit_of_bank_dimension,
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output reg last_bit_of_one_tuple,
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//debug counters
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output wire [2:0] [31:0] formatter_debug_cnt
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);
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reg rst_n_reg;
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wire c_lane_ready;
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always @ (posedge clk) begin
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rst_n_reg <= rst_n;
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end
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assign centroid_cl_ready = c_lane_ready;
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//--------------------split the centroid cache line---------------------//
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//-------------------------ask zeke to check this-----------------------//
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c_lane_splitter c_lane_splitter
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(
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.clk (clk),
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.rst_n (rst_n_reg),
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.num_cluster (num_cluster),
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.data_dim (data_dim),
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.centroid_cl (centroid_cl),
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.centroid_cl_valid (centroid_cl_valid),
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.c_lane_ready (c_lane_ready),
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.centroid_chunk (centroid_chunk),
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.centroid_chunk_valid(centroid_chunk_valid),
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.last_chunk_of_all_centroid(last_chunk_of_all_centroid),
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.last_chunk_of_one_centroid(last_chunk_of_one_centroid) );
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//----------------------re-group the bits of samples----------------------//
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reg [7:0] numBits_index;
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reg [MAX_DEPTH_BITS:0] data_dim_index;
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always @ (posedge clk) begin
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if(~rst_n_reg) begin
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numBits_index <= '0;
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data_dim_index <= '0;
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last_bit_of_bank_dimension <= 1'b0;
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last_bit_of_one_tuple <= 1'b0;
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end
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else begin
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last_bit_of_bank_dimension <= 1'b0;
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last_bit_of_one_tuple <= 1'b0;
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tuple_bit_valid <= 1'b0;
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if(tuple_cl_valid) begin
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for (integer i = 0; i < NUM_PIPELINE; i++) begin
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for (integer j = 0; j < NUM_BANK; j++) begin
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tuple_bit[i][j] <= tuple_cl[j*NUM_PIPELINE+i];
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end
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end
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tuple_bit_valid <= tuple_cl_valid;
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numBits_index <= numBits_index + 1'b1;
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if(numBits_index == precision-1) begin
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numBits_index <= '0;
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last_bit_of_bank_dimension <= 1'b1;
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data_dim_index <= data_dim_index + NUM_BANK; //reduction of NUM_BANK dimensions
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if(data_dim_index + NUM_BANK >= data_dim-1) begin
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data_dim_index <= '0;
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last_bit_of_one_tuple <= 1'b1;
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end
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end
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end
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end
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end
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endmodule
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