84 lines
2.9 KiB
Systemverilog
84 lines
2.9 KiB
Systemverilog
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/*
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* Copyright 2019 - 2020 Systems Group, ETH Zurich
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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module smart_shifter #(parameter ELEMENTS_PER_CL = 16,
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parameter ELEMENTS_PER_CL_BITS = 4)
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(
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input wire clk,
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input wire rst_n,
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input wire inValid,
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input wire inLast,
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input wire [3:0] inOffs,
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input wire [1023:0] inData,
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output wire outValid,
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output wire outLast,
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output reg [511:0] outData
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);
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reg [1023:0] shData [14:0];
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reg [3:0] shOffs [14:0];
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integer i;
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always @(posedge clk) begin
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// Level 0
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if ( |inOffs ) begin
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shData[0] <= {32'b0, inData[1023:32]};
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shOffs[0] <= inOffs - 4'd1;
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end
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else begin
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shData[0] <= inData;
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shOffs[0] <= inOffs;
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end
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// Rest of levels: Data, shOffs
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for ( i = 0; i <14; i = i+1) begin
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if ( |shOffs[i] ) begin
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shData[i+1] <= {32'b0, shData[i][1023:32]};
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shOffs[i+1] <= shOffs[i] - 4'd1;
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end
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else begin
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shData[i+1] <= shData[i];
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shOffs[i+1] <= shOffs[i];
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end
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end
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outData <= shData[14][511:0];
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end
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//
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delay #(.DATA_WIDTH(1),
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.DELAY_CYCLES(16)
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) validDelay(
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.clk (clk),
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.rst_n (rst_n),
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.data_in ( inLast ), //
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.data_in_valid ( inValid ),
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.data_out ( outLast ),
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.data_out_valid ( outValid )
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);
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endmodule
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