443 lines
16 KiB
Systemverilog
443 lines
16 KiB
Systemverilog
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/*
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* Copyright 2019 - 2020 Systems Group, ETH Zurich
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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import DTPackage::*;
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/*
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*/
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module processing_element #(parameter PE_ID = 0 )
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(
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input wire clk,
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input wire rst_n,
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input wire [DATA_LINE_WIDTH-1:0] data_line_in,
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input wire data_line_in_valid,
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input wire data_line_in_last,
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input wire data_line_in_ctrl,
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input wire data_line_in_prog,
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input wire [NUM_PUS_PER_CLUSTER_BITS-1:0] data_line_in_pu,
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output reg data_line_in_ready,
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output reg [DATA_LINE_WIDTH-1:0] data_line_out,
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output reg data_line_out_valid,
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output reg data_line_out_ctrl,
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output reg data_line_out_last,
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output reg data_line_out_prog,
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output reg [NUM_PUS_PER_CLUSTER_BITS-1:0] data_line_out_pu,
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output reg [DATA_PRECISION-1:0] pu_tree_leaf_out,
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output reg pu_tree_leaf_out_valid,
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output reg pu_tree_leaf_out_last
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);
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localparam INSTRUCTION_DELAY = NUM_PUS_PER_CLUSTER - PE_ID - 1; // PU pipeline depth-1 - PU_ID
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localparam TREE_MODE = 1'b0;
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localparam DATA_MODE = 1'b1;
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////////////////////////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////// //////////////////////////////////
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////////////////////////////// Signals Declarations /////////////////////////
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////////////////////////////////////// //////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////////////////////////
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TreeInstruction_t dp_tree_instruction;
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wire dp_tree_instruction_valid;
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wire dp_tree_instruction_ready;
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wire dp_data_mem_ren;
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wire [31:0] dp_data_mem_feature;
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wire [TUPLE_OFFSET_BITS:0] dp_data_mem_rd_addr;
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// tree memory read port A
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wire [TREE_OFFSET_BITS:0] dp_tree_mem_rd_addr_a;
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wire dp_tree_mem_ren_a;
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TreeNode_t dp_tree_node_basic;
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wire [63:0] dp_tree_node_basic_vec;
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// tree memory read port B
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wire [TREE_OFFSET_BITS:0] dp_tree_mem_rd_addr_b;
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wire dp_tree_mem_ren_b;
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wire [31:0] dp_node_large_bitset;
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// result output
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wire [31:0] dp_tree_eval_result;
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wire dp_tree_eval_last;
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wire dp_tree_eval_result_valid;
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reg [1:0] curr_tree_id;
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reg [8:0] curr_tuple_offset;
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reg [9:0] time_stamp;
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reg tuple_old_enough_set;
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wire tuple_instr_fifo_ready;
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wire tuple_instr_fifo_valid;
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wire [9:0] tuple_instr_fifo_dout;
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wire tuple_instr_re;
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wire tuple_old_enough;
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wire curr_feature_done;
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reg [9:0] features_mem_count;
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reg [8:0] features_wr_addr;
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reg [2:0] local_num_trees;
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reg [2:0] local_num_trees_minus_one;
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reg [TREE_OFFSET_BITS-1:0] received_tree_lines;
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reg [TREE_OFFSET_BITS-1:0] tree_prog_addr;
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reg [TREE_OFFSET_BITS-1:0] tree_offsets[3:0];
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wire [TREE_OFFSET_BITS :0] tree_mem_addr_a;
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reg [4:0] num_trees_per_pu_minus_one;
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reg [3:0] tree_depth;
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reg [8:0] num_lines_per_tuple;
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reg [7:0] tree_addra[5:0];
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reg [7:0] tree_addrb[5:0];
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reg [2:0] rd_a_count;
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reg [2:0] rd_b_count;
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reg first_word_correct;
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reg [63:0] first_word;
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reg pe_state;
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reg [63:0] tree_mem_out_a;
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reg [31:0] data_mem_out_a;
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reg tree_out_a_set;
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reg data_out_a_set;
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wire dp_tree_valid_out1;
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wire dp_data_mem_feature_valid;
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////////////////////////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////// //////////////////////////////////
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////////////////////////////// PU Programming Logic /////////////////////////
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////////////////////////////////////// //////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////////////////////////
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always @(posedge clk) begin
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if(~rst_n) begin
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data_line_out_valid <= 0;
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data_line_out_last <= 0;
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data_line_out_ctrl <= 0;
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data_line_out_prog <= 0;
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pe_state <= TREE_MODE;
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end
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else begin
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data_line_out_valid <= data_line_in_valid;
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data_line_out_last <= data_line_in_last;
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data_line_out_ctrl <= data_line_in_ctrl;
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data_line_out_prog <= data_line_in_prog;
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if(data_line_in_valid | (pe_state == DATA_MODE) ) begin
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pe_state <= DATA_MODE;
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end
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end
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//
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data_line_out <= data_line_in;
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data_line_out_pu <= data_line_in_pu;
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end
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always @(posedge clk) begin
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if(~rst_n) begin
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num_trees_per_pu_minus_one <= 5'b0;
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tree_depth <= 4'b0;
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num_lines_per_tuple <= 9'b0;
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end
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else if(data_line_in_ctrl) begin
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num_trees_per_pu_minus_one <= data_line_in[4:0];
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tree_depth <= data_line_in[8+4-1:8];
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num_lines_per_tuple <= data_line_in[16+9-1:16];
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end
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end
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//assign pu_debug_counters = {local_num_trees, received_tree_lines[8:0], tree_offsets[3][8:0], tree_offsets[2][8:0], tree_offsets[1][8:0], tree_offsets[0][8:0]};
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assign pu_debug_counters = {tree_addrb[5], tree_addrb[4], tree_addrb[3], tree_addrb[2], tree_addrb[1], tree_addrb[0], tree_addra[5], tree_addra[4], tree_addra[3], tree_addra[2], tree_addra[1], tree_addra[0]};
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assign pu_debug_counters2 = {tree_mem_out_a[31:0], first_word};
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////////////////////////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////// //////////////////////////////////
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////////////////////////////// Memory Banks /////////////////////////
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////////////////////////////////////// //////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////////////////////////
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genvar j;
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generate for ( j = 0; j < 6; j=j+1) begin
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always@(posedge clk) begin
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if(~rst_n) begin
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tree_addra[j] <= 0;
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tree_addrb[j] <= 0;
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end
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else begin
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if(dp_tree_mem_ren_a && (rd_a_count == j)) begin
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tree_addra[j] <= tree_mem_addr_a[7:0];
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end
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if(dp_tree_mem_ren_b && (rd_b_count == j)) begin
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tree_addrb[j] <= dp_tree_mem_rd_addr_b[7:0];
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end
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end
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end
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end
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endgenerate
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integer i;
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always@(posedge clk) begin
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if(~rst_n) begin
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rd_a_count <= 0;
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rd_b_count <= 0;
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tree_mem_out_a <= 0;
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data_mem_out_a <= 0;
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tree_out_a_set <= 1'b0;
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data_out_a_set <= 1'b0;
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first_word_correct <= 0;
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first_word <= 0;
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end
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else begin
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if(dp_tree_mem_ren_a && rd_a_count < 6) begin
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rd_a_count <= rd_a_count + 1'b1;
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end
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if(dp_tree_mem_ren_b && rd_b_count < 6) begin
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rd_b_count <= rd_b_count + 1'b1;
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end
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//
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if(dp_tree_valid_out1 && ~tree_out_a_set) begin
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tree_mem_out_a <= dp_tree_node_basic_vec;
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tree_out_a_set <= 1'b1;
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end
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if(dp_data_mem_feature_valid && ~data_out_a_set) begin
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data_mem_out_a <= dp_data_mem_feature;
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data_out_a_set <= 1'b1;
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end
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//
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if((tree_prog_addr == 0) && (data_line_in_prog && (data_line_in_pu == PE_ID) )) begin
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first_word_correct <= data_line_in[15:0] == 16'h200c;
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first_word <= data_line_in;
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end
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end
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end
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//----------------------------- Tree Nodes Weight memory ------------------------------//
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Tree_Memory #( .DATA_WIDTH(64),
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.ADDR_WIDTH(11) )
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TreeNodes(
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.clk ( clk ),
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.rst_n ( rst_n ),
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.we ( data_line_in_prog && (data_line_in_pu == PE_ID) ),
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.rea ( dp_tree_mem_ren_a ),
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.reb ( dp_tree_mem_ren_b ),
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.addr_port_a ( tree_mem_addr_a ),
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.addr_port_b ( dp_tree_mem_rd_addr_b ),
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.din ( data_line_in ),
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.dout1 ( dp_tree_node_basic_vec ),
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.valid_out1 ( dp_tree_valid_out1),
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.dout2 ( dp_node_large_bitset ),
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.valid_out2 ()
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);
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assign dp_tree_node_basic.word_1_h = dp_tree_node_basic_vec[63:48];
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assign dp_tree_node_basic.word_1_l = dp_tree_node_basic_vec[47:32];
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assign dp_tree_node_basic.right_child_offset = dp_tree_node_basic_vec[31:16];
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assign dp_tree_node_basic.node_type.op_type = dp_tree_node_basic_vec[1:0];
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assign dp_tree_node_basic.node_type.left_child = dp_tree_node_basic_vec[2];
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assign dp_tree_node_basic.node_type.right_child = dp_tree_node_basic_vec[3];
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assign dp_tree_node_basic.node_type.findex = dp_tree_node_basic_vec[11:4];
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assign dp_tree_node_basic.node_type.split_dir = dp_tree_node_basic_vec[15:12];
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assign tree_mem_addr_a = ( pe_state == TREE_MODE )? {tree_prog_addr, 1'b0} : dp_tree_mem_rd_addr_a;
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always @(posedge clk) begin
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//
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if(~rst_n) begin
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tree_prog_addr <= 0;
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local_num_trees <= 0;
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received_tree_lines <= 0;
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local_num_trees_minus_one <= 0;
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for (i = 0; i < 4; i++) begin
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tree_offsets[ i ] <= 0;
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end
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end
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else begin
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local_num_trees_minus_one <= local_num_trees;
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//
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if(data_line_in_prog && (data_line_in_pu == PE_ID)) begin
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tree_prog_addr <= tree_prog_addr + 1'b1;
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received_tree_lines <= received_tree_lines + 1'b1;
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if(data_line_in_last && (local_num_trees[1:0] < num_trees_per_pu_minus_one[1:0])) begin
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tree_offsets[ local_num_trees[1:0] + 1'b1 ] <= received_tree_lines + 1'b1;
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local_num_trees <= local_num_trees + 1'b1;
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end
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end
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end
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end
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//--------------------------- Input tuple features memory -----------------------------//
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/* We write to the features memory when flags indicate incoming data is tuples and not programming data
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*/
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Data_Memory #( .DATA_WIDTH(64),
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.ADDR_WIDTH(10) )
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SamplesFeatures_Mem(
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.clk (clk),
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.rst_n (rst_n),
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.we (data_line_in_valid),
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.re (dp_data_mem_ren),
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.raddr (dp_data_mem_rd_addr),
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.waddr (features_wr_addr),
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.din (data_line_in),
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.dout (dp_data_mem_feature),
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.valid_out (dp_data_mem_feature_valid)
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);
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always @(posedge clk) begin
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if(~rst_n) begin
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features_wr_addr <= 9'b0;
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features_mem_count <= 0;
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end
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else begin
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features_wr_addr <= features_wr_addr + ((data_line_in_valid)? 9'd1 : 9'd0);
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features_mem_count <= features_mem_count + ((data_line_in_valid)? 9'd1 : 9'd0) - ((curr_feature_done)? num_lines_per_tuple : 9'b0);
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end
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end
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assign curr_feature_done = dp_tree_eval_result_valid & dp_tree_eval_last;
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assign data_line_in_ready = tuple_instr_fifo_ready & (features_mem_count < (512- PE_ID - 1));
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////////////////////////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////// //////////////////////////////////
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////////////////////////////// Tuple Instruction FIFO /////////////////////////
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////////////////////////////////////// //////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////////////////////////
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/* Once all features of a tuple are in features memory, we enqueue an instruction to execute all the
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trees in the PU on the current tuple features, the instruction simply include the tuple offset.
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*/
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RegBasedFIFO #(.FIFO_WIDTH(10),
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.FIFO_DEPTH_BITS(2)
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) tuple_instr_fifo (
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.clk (clk),
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.rst_n (rst_n),
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.data_in ( time_stamp ),
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.data_in_valid ( data_line_in_valid && data_line_in_last ),
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.data_out_ready (tuple_instr_re),
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.data_out (tuple_instr_fifo_dout),
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.data_out_valid (tuple_instr_fifo_valid),
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.data_in_ready (tuple_instr_fifo_ready)
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);
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assign tuple_instr_re = dp_tree_instruction_ready && (tuple_old_enough || tuple_old_enough_set) && (curr_tree_id == num_trees_per_pu_minus_one);
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assign tuple_old_enough = tuple_instr_fifo_valid && ((time_stamp <= tuple_instr_fifo_dout) || ((time_stamp - tuple_instr_fifo_dout) > INSTRUCTION_DELAY));
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assign dp_tree_instruction_valid = tuple_instr_fifo_valid && (tuple_old_enough || tuple_old_enough_set);
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assign dp_tree_instruction = '{tree_offset: tree_offsets[curr_tree_id],
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tuple_offset: curr_tuple_offset,
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last_tree: (curr_tree_id == num_trees_per_pu_minus_one),
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empty_tree: (curr_tree_id > local_num_trees)};
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// Flags, counters used in issuing tree instructions to the datapath and synchronizing logic with other PEs.
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always @(posedge clk) begin
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if(~rst_n) begin
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time_stamp <= 0;
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tuple_old_enough_set <= 0;
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curr_tuple_offset <= 0;
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curr_tree_id <= 0;
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end
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else begin
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// tuple_old_enough_set
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tuple_old_enough_set <= (tuple_instr_re && tuple_instr_fifo_valid)? 1'b0 : (tuple_old_enough_set || tuple_old_enough);
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// time_stamp
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time_stamp <= time_stamp + 1'b1;
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// curr_tuple_offset
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if(tuple_instr_fifo_valid && tuple_instr_re) begin
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curr_tuple_offset <= curr_tuple_offset + num_lines_per_tuple;
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end
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// curr_tree_id
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if(tuple_instr_fifo_valid && dp_tree_instruction_ready && (tuple_old_enough || tuple_old_enough_set)) begin
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if(curr_tree_id == num_trees_per_pu_minus_one) begin
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curr_tree_id <= 0;
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end
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else begin
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curr_tree_id <= curr_tree_id + 1'b1;
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end
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end
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end
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end
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////////////////////////////////////////////////////////////////////////////////////////////////////
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// PE Datapath
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pe_datapath pe_datapath(
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.clk (clk),
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.rst_n (rst_n),
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.tree_depth (tree_depth),
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// tree instruction
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.tree_instruction (dp_tree_instruction),
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.tree_instruction_valid (dp_tree_instruction_valid),
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.tree_instruction_ready (dp_tree_instruction_ready),
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// data memory read port
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.data_mem_rd_addr (dp_data_mem_rd_addr),
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.data_mem_ren (dp_data_mem_ren),
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.data_mem_feature (dp_data_mem_feature),
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// tree memory read port A
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.tree_mem_rd_addr_a (dp_tree_mem_rd_addr_a),
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.tree_mem_ren_a (dp_tree_mem_ren_a),
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.tree_node_basic (dp_tree_node_basic),
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// tree memory read port B
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.tree_mem_rd_addr_b (dp_tree_mem_rd_addr_b),
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.tree_mem_ren_b (dp_tree_mem_ren_b),
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.node_large_bitset (dp_node_large_bitset),
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// result output
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.tree_eval_result (dp_tree_eval_result),
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.tree_eval_last (dp_tree_eval_last),
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.tree_eval_result_valid (dp_tree_eval_result_valid)
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);
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always @(posedge clk) begin
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if(~rst_n) begin
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pu_tree_leaf_out <= 0;
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pu_tree_leaf_out_last <= 0;
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pu_tree_leaf_out_valid <= 0;
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end
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else begin
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pu_tree_leaf_out <= dp_tree_eval_result;
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pu_tree_leaf_out_last <= dp_tree_eval_last;
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pu_tree_leaf_out_valid <= dp_tree_eval_result_valid;
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end
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end
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endmodule // DTPU
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