293 lines
7.9 KiB
Systemverilog
293 lines
7.9 KiB
Systemverilog
/**
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* GBM slave
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*/
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import lynxTypes::*;
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module gbm_slave #(
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parameter integer NFEAUTRES_BITS = 16,
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parameter integer TREEDEPTH_BITS = 8,
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parameter integer PUTREES_BITS = 8,
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parameter integer OUTNUMCLS_BITS = 32,
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parameter integer LSTOUTMASK_BITS = 16
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) (
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input logic aclk,
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input logic aresetn,
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AXI4L.s axi_ctrl,
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// User defined arguments
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output logic ap_start,
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output logic [NFEAUTRES_BITS-1:0] numFeatures,
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output logic [TREEDEPTH_BITS-1:0] treeDepth,
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output logic [PUTREES_BITS-1:0] puTrees,
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output logic [OUTNUMCLS_BITS-1:0] outputNumCLs,
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output logic [LSTOUTMASK_BITS-1:0] lastOutLineMask
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);
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// -- Decl ----------------------------------------------------------
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// ------------------------------------------------------------------
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// Constants
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localparam integer N_REGS = 6;
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localparam integer ADDR_LSB = $clog2(AXIL_DATA_BITS/8);
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localparam integer ADDR_MSB = $clog2(N_REGS);
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localparam integer AXIL_ADDR_BITS = ADDR_LSB + ADDR_MSB;
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// Internal registers
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logic [AXIL_ADDR_BITS-1:0] axi_awaddr;
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logic axi_awready;
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logic [AXIL_ADDR_BITS-1:0] axi_araddr;
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logic axi_arready;
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logic [1:0] axi_bresp;
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logic axi_bvalid;
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logic axi_wready;
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logic [AXIL_DATA_BITS-1:0] axi_rdata;
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logic [1:0] axi_rresp;
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logic axi_rvalid;
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// Registers
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logic [N_REGS-1:0][AXIL_DATA_BITS-1:0] slv_reg;
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logic slv_reg_rden;
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logic slv_reg_wren;
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logic aw_en;
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// -- Def -----------------------------------------------------------
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// ------------------------------------------------------------------
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// -- Register map -----------------------------------------------------------------------
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// 0 (W1S) : AP start (
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localparam integer AP_CTRL_REG = 0;
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// 0 - start
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// 1 (WR) : Number of features
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localparam integer NFEAUTERS_REG = 1;
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// 2 (WR) : Treedepth
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localparam integer TREEDEPTH_REG = 2;
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// 3 (WR) : Putrees
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localparam integer PUTREES_REG = 3;
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// 4 (WR) : OutputNumCLs
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localparam integer OUTNUMCLS_REG = 4;
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// 5 (WR) : LastOutLineMask
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localparam integer LSTOUTMASK_REG = 5;
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// Write process
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assign slv_reg_wren = axi_wready && axi_ctrl.wvalid && axi_awready && axi_ctrl.awvalid;
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always_ff @(posedge aclk) begin
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if ( aresetn == 1'b0 ) begin
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slv_reg <= 0;
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end
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else begin
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// Control
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slv_reg[AP_CTRL_REG] <= 0;
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if(slv_reg_wren) begin
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case (axi_awaddr[ADDR_LSB+:ADDR_MSB])
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AP_CTRL_REG: // Control
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for (int i = 0; i < (AXIL_DATA_BITS/8); i++) begin
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if(axi_ctrl.wstrb[i]) begin
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slv_reg[AP_CTRL_REG][(i*8)+:8] <= axi_ctrl.wdata[(i*8)+:8];
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end
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end
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NFEAUTERS_REG: // Number of features
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for (int i = 0; i < (AXIL_DATA_BITS/8); i++) begin
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if(axi_ctrl.wstrb[i]) begin
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slv_reg[NFEAUTERS_REG][(i*8)+:8] <= axi_ctrl.wdata[(i*8)+:8];
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end
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end
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TREEDEPTH_REG: // Treedepth
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for (int i = 0; i < (AXIL_DATA_BITS/8); i++) begin
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if(axi_ctrl.wstrb[i]) begin
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slv_reg[TREEDEPTH_REG][(i*8)+:8] <= axi_ctrl.wdata[(i*8)+:8];
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end
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end
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PUTREES_REG: // Putrees
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for (int i = 0; i < (AXIL_DATA_BITS/8); i++) begin
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if(axi_ctrl.wstrb[i]) begin
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slv_reg[PUTREES_REG][(i*8)+:8] <= axi_ctrl.wdata[(i*8)+:8];
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end
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end
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OUTNUMCLS_REG: // Output number of CLs
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for (int i = 0; i < (AXIL_DATA_BITS/8); i++) begin
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if(axi_ctrl.wstrb[i]) begin
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slv_reg[OUTNUMCLS_REG][(i*8)+:8] <= axi_ctrl.wdata[(i*8)+:8];
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end
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end
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LSTOUTMASK_REG: // Last out line mask
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for (int i = 0; i < (AXIL_DATA_BITS/8); i++) begin
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if(axi_ctrl.wstrb[i]) begin
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slv_reg[LSTOUTMASK_REG][(i*8)+:8] <= axi_ctrl.wdata[(i*8)+:8];
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end
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end
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default : ;
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endcase
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end
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end
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end
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// Read process
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assign slv_reg_rden = axi_arready & axi_ctrl.arvalid & ~axi_rvalid;
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always_ff @(posedge aclk) begin
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if( aresetn == 1'b0 ) begin
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axi_rdata <= 0;
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end
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else begin
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if(slv_reg_rden) begin
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axi_rdata <= 0;
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case (axi_araddr[ADDR_LSB+:ADDR_MSB])
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NFEAUTERS_REG: // Key low
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axi_rdata[NFEAUTRES_BITS-1:0] <= slv_reg[NFEAUTERS_REG][NFEAUTRES_BITS-1:0];
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TREEDEPTH_REG: // Key high
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axi_rdata[TREEDEPTH_BITS-1:0] <= slv_reg[TREEDEPTH_REG][TREEDEPTH_BITS-1:0];
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PUTREES_REG: // Key high
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axi_rdata[PUTREES_BITS-1:0] <= slv_reg[PUTREES_REG][PUTREES_BITS-1:0];
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OUTNUMCLS_REG: // Key high
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axi_rdata[OUTNUMCLS_BITS-1:0] <= slv_reg[OUTNUMCLS_REG][OUTNUMCLS_BITS-1:0];
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LSTOUTMASK_REG: // Key high
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axi_rdata[LSTOUTMASK_BITS-1:0] <= slv_reg[LSTOUTMASK_REG][LSTOUTMASK_BITS-1:0];
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default: ;
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endcase
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end
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end
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end
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// Output
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always_comb begin
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ap_start = slv_reg[AP_CTRL_REG][0];
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numFeatures = slv_reg[NFEAUTERS_REG][15:0];
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treeDepth = slv_reg[TREEDEPTH_REG][7:0];
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puTrees = slv_reg[PUTREES_REG][7:0];
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outputNumCLs = slv_reg[OUTNUMCLS_REG][31:0];
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lastOutLineMask = slv_reg[LSTOUTMASK_REG][15:0];
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end
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// --------------------------------------------------------------------------------------
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// AXI CTRL
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// --------------------------------------------------------------------------------------
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// Don't edit
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// I/O
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assign axi_ctrl.awready = axi_awready;
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assign axi_ctrl.arready = axi_arready;
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assign axi_ctrl.bresp = axi_bresp;
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assign axi_ctrl.bvalid = axi_bvalid;
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assign axi_ctrl.wready = axi_wready;
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assign axi_ctrl.rdata = axi_rdata;
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assign axi_ctrl.rresp = axi_rresp;
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assign axi_ctrl.rvalid = axi_rvalid;
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// awready and awaddr
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always_ff @(posedge aclk) begin
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if ( aresetn == 1'b0 )
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begin
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axi_awready <= 1'b0;
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axi_awaddr <= 0;
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aw_en <= 1'b1;
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end
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else
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begin
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if (~axi_awready && axi_ctrl.awvalid && axi_ctrl.wvalid && aw_en)
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begin
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axi_awready <= 1'b1;
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aw_en <= 1'b0;
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axi_awaddr <= axi_ctrl.awaddr;
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end
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else if (axi_ctrl.bready && axi_bvalid)
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begin
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aw_en <= 1'b1;
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axi_awready <= 1'b0;
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end
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else
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begin
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axi_awready <= 1'b0;
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end
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end
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end
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// arready and araddr
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always_ff @(posedge aclk) begin
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if ( aresetn == 1'b0 )
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begin
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axi_arready <= 1'b0;
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axi_araddr <= 0;
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end
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else
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begin
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if (~axi_arready && axi_ctrl.arvalid)
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begin
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axi_arready <= 1'b1;
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axi_araddr <= axi_ctrl.araddr;
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end
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else
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begin
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axi_arready <= 1'b0;
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end
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end
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end
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// bvalid and bresp
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always_ff @(posedge aclk) begin
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if ( aresetn == 1'b0 )
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begin
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axi_bvalid <= 0;
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axi_bresp <= 2'b0;
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end
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else
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begin
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if (axi_awready && axi_ctrl.awvalid && ~axi_bvalid && axi_wready && axi_ctrl.wvalid)
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begin
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axi_bvalid <= 1'b1;
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axi_bresp <= 2'b0;
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end
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else
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begin
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if (axi_ctrl.bready && axi_bvalid)
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begin
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axi_bvalid <= 1'b0;
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end
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end
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end
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end
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// wready
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always_ff @(posedge aclk) begin
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if ( aresetn == 1'b0 )
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begin
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axi_wready <= 1'b0;
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end
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else
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begin
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if (~axi_wready && axi_ctrl.wvalid && axi_ctrl.awvalid && aw_en )
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begin
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axi_wready <= 1'b1;
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end
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else
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begin
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axi_wready <= 1'b0;
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end
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end
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end
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// rvalid and rresp (1Del?)
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always_ff @(posedge aclk) begin
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if ( aresetn == 1'b0 )
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begin
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axi_rvalid <= 0;
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axi_rresp <= 0;
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end
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else
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begin
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if (axi_arready && axi_ctrl.arvalid && ~axi_rvalid)
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begin
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axi_rvalid <= 1'b1;
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axi_rresp <= 2'b0;
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end
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else if (axi_rvalid && axi_ctrl.rready)
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begin
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axi_rvalid <= 1'b0;
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end
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end
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end
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endmodule // gbm slave
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