122 lines
3.3 KiB
Systemverilog
122 lines
3.3 KiB
Systemverilog
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/*
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* Copyright 2019 - 2020 Systems Group, ETH Zurich
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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module RegBasedFIFO #(parameter FIFO_WIDTH = 32,
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parameter FIFO_DEPTH_BITS = 2
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)(
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input wire clk,
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input wire rst_n,
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input wire [FIFO_WIDTH-1:0] data_in,
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input wire data_in_valid,
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output wire data_in_ready,
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output wire [FIFO_WIDTH-1:0] data_out,
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output wire data_out_valid,
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input wire data_out_ready
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);
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localparam FIFO_NUM_REGS = 2**FIFO_DEPTH_BITS;
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reg [FIFO_WIDTH-1:0] fifo_reg_data[FIFO_NUM_REGS-1:0];
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reg fifo_reg_valid[FIFO_NUM_REGS-1:0];
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// Last Reg in the FIFO
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// valid
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always@(posedge clk) begin
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// data
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if(data_out_ready || ~fifo_reg_valid[FIFO_NUM_REGS-1]) begin
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fifo_reg_data[FIFO_NUM_REGS-1] <= data_in;
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end
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// valid
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if(~rst_n) begin
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fifo_reg_valid[FIFO_NUM_REGS-1] <= 1'b0;
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end
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else begin
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if(data_out_ready) begin
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fifo_reg_valid[FIFO_NUM_REGS-1] <= 1'b0;
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end
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else if(!fifo_reg_valid[FIFO_NUM_REGS-1] && fifo_reg_valid[FIFO_NUM_REGS-2]) begin
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fifo_reg_valid[FIFO_NUM_REGS-1] <= data_in_valid;
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end
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end
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end
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// Rest of Regs
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genvar i;
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generate for (i = 0; i < FIFO_NUM_REGS-1; i=i+1) begin: fifo_regs
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// valid
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always@(posedge clk) begin
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// Data
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if(~fifo_reg_valid[i]) begin
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fifo_reg_data[i] <= data_in;
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end
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else if(data_out_ready) begin
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if(fifo_reg_valid[i+1]) begin
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fifo_reg_data[i] <= fifo_reg_data[i+1];
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end
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else begin
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fifo_reg_data[i] <= data_in;
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end
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end
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// valid
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if(~rst_n) begin
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fifo_reg_valid[i] <= 1'b0;
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end
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else if(~fifo_reg_valid[i]) begin
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if(i == 0) begin
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fifo_reg_valid[i] <= data_in_valid;
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end
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else begin
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if(!data_out_ready && fifo_reg_valid[i-1]) begin
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fifo_reg_valid[i] <= data_in_valid;
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end
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end
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end
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else if(data_out_ready) begin
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if(fifo_reg_valid[i+1]) begin
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fifo_reg_valid[i] <= 1'b1;
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end
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else begin
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fifo_reg_valid[i] <= data_in_valid;
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end
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end
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end
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end
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endgenerate
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//
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assign data_in_ready = ~fifo_reg_valid[FIFO_NUM_REGS-2];
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assign data_out = fifo_reg_data[0];
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assign data_out_valid = fifo_reg_valid[0];
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endmodule |