134 lines
5.1 KiB
Systemverilog
134 lines
5.1 KiB
Systemverilog
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/*
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* Copyright 2019 - 2020 Systems Group, ETH Zurich
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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import DTPackage::*;
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module LineRateConvertor #(parameter CU_ID = 0 )
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(
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input wire clk,
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input wire rst_n,
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input wire [511:0] data_line_in,
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input wire data_line_in_valid,
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input wire [2:0] data_line_in_last_valid_pos,
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input wire data_line_in_last,
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input wire data_line_in_ctrl,
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input wire data_line_in_prog,
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input wire [NUM_PUS_PER_CLUSTER_BITS-1:0] data_line_in_pu,
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input wire [NUM_DTPU_CLUSTERS_BITS-1:0] data_line_in_cu,
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output wire data_line_in_ready,
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output reg [DATA_LINE_WIDTH-1:0] data_line_out,
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output reg data_line_out_valid,
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output reg data_line_out_ctrl,
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output reg data_line_out_last,
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output reg data_line_out_prog,
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output reg [NUM_PUS_PER_CLUSTER_BITS-1:0] data_line_out_pu,
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input wire data_line_out_ready
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);
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wire data_line_fifo_we;
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wire data_line_fifo_almfull;
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wire data_line_fifo_valid;
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wire data_line_fifo_re;
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wire [63:0] data_line_array[7:0];
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wire [511:0] data_line_in_fifo_data;
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wire data_line_in_fifo_valid;
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wire [2:0] data_line_in_fifo_last_valid_pos;
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wire data_line_in_fifo_last;
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wire data_line_in_fifo_ctrl;
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wire data_line_in_fifo_prog;
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wire [NUM_PUS_PER_CLUSTER_BITS-1:0] data_line_in_fifo_pu;
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reg [2:0] curr_word;
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/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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assign data_line_fifo_we = (data_line_in_valid && (data_line_in_cu == CU_ID)) || data_line_in_ctrl || data_line_in_prog;
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assign data_line_in_ready = ~data_line_fifo_almfull;
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// Input Line FIFO
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quick_fifo #(.FIFO_WIDTH(512+3+1+1+1+1+5),
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.FIFO_DEPTH_BITS(9),
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.FIFO_ALMOSTFULL_THRESHOLD(500)
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) data_line_fifo (
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.clk (clk),
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.reset_n (rst_n),
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.din ({data_line_in_pu, data_line_in_prog, data_line_in_ctrl, data_line_in_last, data_line_in_valid, data_line_in_last_valid_pos, data_line_in}),
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.we (data_line_fifo_we),
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.re (data_line_fifo_re),
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.dout ({data_line_in_fifo_pu, data_line_in_fifo_prog, data_line_in_fifo_ctrl, data_line_in_fifo_last, data_line_in_fifo_valid, data_line_in_fifo_last_valid_pos, data_line_in_fifo_data}),
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.empty (),
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.valid (data_line_fifo_valid),
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.full (),
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.count (),
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.almostfull (data_line_fifo_almfull)
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);
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// Put the input data line in an array
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genvar i;
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generate for (i = 0; i < 8; i=i+1) begin
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assign data_line_array[i] = data_line_in_fifo_data[64*i+63:64*i];
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end
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endgenerate
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// Select output 64-bit word
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always@(posedge clk) begin
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data_line_out <= data_line_array[ curr_word ];
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data_line_out_valid <= data_line_fifo_valid && data_line_in_fifo_valid && data_line_out_ready;
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data_line_out_last <= data_line_in_fifo_last && (curr_word == data_line_in_fifo_last_valid_pos);
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data_line_out_ctrl <= data_line_fifo_valid && data_line_in_fifo_ctrl;
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data_line_out_prog <= data_line_fifo_valid && data_line_in_fifo_prog;
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data_line_out_pu <= data_line_in_fifo_pu;
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end
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// data_line_fifo_re
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assign data_line_fifo_re = data_line_out_ready && ( (data_line_in_fifo_last && (curr_word == data_line_in_fifo_last_valid_pos)) || (curr_word == 3'b111) );
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// curr_word calculation
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always@(posedge clk) begin
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if(~rst_n) begin
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curr_word <= 3'b000;
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end
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else begin
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if(data_line_out_ready && data_line_fifo_valid) begin
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if(data_line_in_fifo_last && (curr_word == data_line_in_fifo_last_valid_pos) ) begin
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curr_word <= 3'b000;
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end
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else if(curr_word == 3'b111) begin
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curr_word <= 3'b000;
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end
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else begin
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curr_word <= curr_word + 1'b1;
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end
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end
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end
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end
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endmodule |