390 lines
12 KiB
Systemverilog
390 lines
12 KiB
Systemverilog
// File 2cycles_latency.vhdl translated with vhd2vl v2.4 VHDL to Verilog RTL translator
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// vhd2vl settings:
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// * Verilog Module Declaration Style: 1995
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// vhd2vl is Free (libre) Software:
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// Copyright (C) 2001 Vincenzo Liguori - Ocean Logic Pty Ltd
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// http://www.ocean-logic.com
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// Modifications Copyright (C) 2006 Mark Gonzales - PMC Sierra Inc
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// Modifications (C) 2010 Shankar Giri
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// Modifications Copyright (C) 2002, 2005, 2008-2010 Larry Doolittle - LBNL
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// http://doolittle.icarus.com/~larry/vhd2vl/
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//
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// vhd2vl comes with ABSOLUTELY NO WARRANTY. Always check the resulting
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// Verilog for correctness, ideally with a formal verification tool.
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//
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// You are welcome to redistribute vhd2vl under certain conditions.
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// See the license (GPLv2) file included with the source for details.
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// The result of translation follows. Its copyright status should be
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// considered unchanged from the original VHDL.
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//------------------------------------------------------------------------------
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// FPAdder_8_23_uid2_RightShifter
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// (RightShifter_24_by_max_26_uid4)
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// This operator is part of the Infinite Virtual Library FloPoCoLib
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// and is distributed under the terms of the GNU Lesser General Public Licence
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// with a Tobin Tax restriction (see README file for details).
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// Authors: Florent de Dinechin, Bogdan Pasca (2007,2008,2009,2010)
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//------------------------------------------------------------------------------
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// no timescale needed
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module FPAdder_8_23_uid2_RightShifter_l2(
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X,
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S,
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R
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);
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input [23:0] X;
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input [4:0] S;
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output [49:0] R;
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wire clk;
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wire rst;
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wire [23:0] X;
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wire [4:0] S;
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wire [49:0] R;
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wire [23:0] level0;
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wire [4:0] ps;
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wire [24:0] level1;
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wire [26:0] level2;
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wire [30:0] level3;
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wire [38:0] level4;
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wire [54:0] level5;
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assign level0 = X;
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assign ps = S;
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assign level1 = ps[0] == 1'b1 ? {1'b0,level0} : {level0,1'b0};
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assign level2 = ps[1] == 1'b1 ? {2'b00,level1} : {level1,2'b00};
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assign level3 = ps[2] == 1'b1 ? {4'b0000,level2} : {level2,4'b0000};
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assign level4 = ps[3] == 1'b1 ? {8'b00000000,level3} : {level3,8'b00000000};
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assign level5 = ps[4] == 1'b1 ? {16'b0000000000000000,level4} : {level4,16'b0000000000000000};
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assign R = level5[54:5];
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endmodule
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//------------------------------------------------------------------------------
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// IntAdder_27_f110_uid6
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// This operator is part of the Infinite Virtual Library FloPoCoLib
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// and is distributed under the terms of the GNU Lesser General Public Licence
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// with a Tobin Tax restriction (see README file for details).
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// Authors: Bogdan Pasca, Florent de Dinechin (2008-2010)
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//------------------------------------------------------------------------------
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// Pipeline depth: 0 cycles
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// no timescale needed
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module IntAdder_27_f110_uid6_l2(
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X,
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Y,
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Cin,
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R
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);
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input [26:0] X;
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input [26:0] Y;
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input Cin;
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output [26:0] R;
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wire clk;
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wire rst;
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wire [26:0] X;
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wire [26:0] Y;
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wire Cin;
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wire [26:0] R;
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//Alternative
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assign R = X + Y + Cin;
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//------------------------------------------------------------------------------
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// LZCShifter_28_to_28_counting_32_uid16
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// This operator is part of the Infinite Virtual Library FloPoCoLib
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// and is distributed under the terms of the GNU Lesser General Public Licence
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// with a Tobin Tax restriction (see README file for details).
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// Authors: Florent de Dinechin, Bogdan Pasca (2007)
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//------------------------------------------------------------------------------
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// Pipeline depth: 1 cycles
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endmodule
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module LZCShifter_28_to_28_counting_32_uid16_l2(
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clk,
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stall,
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I,
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Count,
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O
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);
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input clk, stall;
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input [27:0] I;
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output [4:0] Count;
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output [27:0] O;
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wire clk;
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wire rst;
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wire [27:0] I;
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wire [4:0] Count;
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wire [27:0] O;
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wire [27:0] level5;
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wire count4; reg count4_d1;
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wire [27:0] level4;
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wire count3; reg count3_d1;
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wire [27:0] level3;
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wire count2; reg count2_d1;
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wire [27:0] level2; reg [27:0] level2_d1;
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wire count1;
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wire [27:0] level1;
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wire count0;
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wire [27:0] level0;
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wire [4:0] sCount;
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always @(posedge clk) begin
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if( ~stall ) begin
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count4_d1 <= count4;
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count3_d1 <= count3;
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count2_d1 <= count2;
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level2_d1 <= level2;
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end
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end
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assign level5 = I;
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assign count4 = level5[27:12] == 16'b0000000000000000 ? 1'b1 : 1'b0;
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assign level4 = count4 == 1'b0 ? level5[27:0] : {level5[11:0],16'b0000000000000000};
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assign count3 = level4[27:20] == 8'b00000000 ? 1'b1 : 1'b0;
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assign level3 = count3 == 1'b0 ? level4[27:0] : {level4[19:0],8'b00000000};
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assign count2 = level3[27:24] == 4'b0000 ? 1'b 1 : 1'b0;
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assign level2 = count2 == 1'b0 ? level3[27:0] : {level3[23:0],4'b0000};
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//--------------Synchro barrier, entering cycle 1----------------
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assign count1 = level2_d1[27:26] == 2'b00 ? 1'b1 : 1'b0;
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assign level1 = count1 == 1'b0 ? level2_d1[27:0] : {level2_d1[25:0],2'b00};
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assign count0 = level1[27:27] == 1'b0 ? 1'b1 : 1'b0;
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assign level0 = count0 == 1'b0 ? level1[27:0] : {level1[26:0],1'b0};
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assign O = level0;
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assign sCount = {count4_d1,count3_d1,count2_d1,count1,count0};
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assign Count = sCount;
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//------------------------------------------------------------------------------
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// IntAdder_34_f110_uid18
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// This operator is part of the Infinite Virtual Library FloPoCoLib
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// and is distributed under the terms of the GNU Lesser General Public Licence
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// with a Tobin Tax restriction (see README file for details).
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// Authors: Bogdan Pasca, Florent de Dinechin (2008-2010)
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//------------------------------------------------------------------------------
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// Pipeline depth: 0 cycles
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endmodule
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module IntAdder_34_f110_uid18_l2(
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X,
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Y,
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Cin,
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R
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);
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input [33:0] X;
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input [33:0] Y;
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input Cin;
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output [33:0] R;
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wire [33:0] X;
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wire [33:0] Y;
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wire Cin;
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wire [33:0] R;
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//Alternative
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assign R = X + Y + Cin;
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//------------------------------------------------------------------------------
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// FPAdder_8_23_uid2
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// This operator is part of the Infinite Virtual Library FloPoCoLib
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// and is distributed under the terms of the GNU Lesser General Public Licence
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// with a Tobin Tax restriction (see README file for details).
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// Authors: Bogdan Pasca, Florent de Dinechin (2010)
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//------------------------------------------------------------------------------
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// Pipeline depth: 2 cycles
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endmodule
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module FPAdder_8_23_uid2_l2(
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clk,
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rst,
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seq_stall,
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X,
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Y,
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R
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);
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input clk, rst;
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input seq_stall;
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input [8 + 23 + 2:0] X;
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input [8 + 23 + 2:0] Y;
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output [8 + 23 + 2:0] R;
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wire clk;
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wire rst;
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wire [8 + 23 + 2:0] X;
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wire [8 + 23 + 2:0] Y;
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wire [8 + 23 + 2:0] R;
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wire [32:0] excExpFracX;
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wire [32:0] excExpFracY;
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wire [8:0] eXmeY;
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wire [8:0] eYmeX;
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wire swap;
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wire [33:0] newX; reg [33:0] newX_d1;
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wire [33:0] newY;
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wire [7:0] expX; reg [7:0] expX_d1;
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wire [1:0] excX;
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wire [1:0] excY;
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wire signX;
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wire signY;
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wire EffSub; reg EffSub_d1; reg EffSub_d2;
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wire [5:0] sdsXsYExnXY;
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wire [3:0] sdExnXY;
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wire [23:0] fracY;
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reg [1:0] excRt; reg [1:0] excRt_d1; reg [1:0] excRt_d2;
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wire signR; reg signR_d1; reg signR_d2;
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wire [8:0] expDiff;
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wire shiftedOut;
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wire [4:0] shiftVal;
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wire [49:0] shiftedFracY; reg [49:0] shiftedFracY_d1;
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wire sticky;
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wire [26:0] fracYfar;
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wire [26:0] fracYfarXorOp;
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wire [26:0] fracXfar;
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wire cInAddFar;
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wire [26:0] fracAddResult;
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wire [27:0] fracGRS;
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wire [9:0] extendedExpInc; reg [9:0] extendedExpInc_d1;
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wire [4:0] nZerosNew;
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wire [27:0] shiftedFrac;
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wire [9:0] updatedExp;
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wire eqdiffsign;
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wire [33:0] expFrac;
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wire stk;
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wire rnd;
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wire grd;
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wire lsb;
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wire addToRoundBit;
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wire [33:0] RoundedExpFrac;
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wire [1:0] upExc;
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wire [22:0] fracR;
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wire [7:0] expR;
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wire [3:0] exExpExc;
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reg [1:0] excRt2;
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wire [1:0] excR;
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wire [33:0] computedR;
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always @(posedge clk) begin
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if( ~seq_stall)begin
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newX_d1 <= newX;
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expX_d1 <= expX;
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EffSub_d1 <= EffSub;
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EffSub_d2 <= EffSub_d1;
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excRt_d1 <= excRt;
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excRt_d2 <= excRt_d1;
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signR_d1 <= signR;
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signR_d2 <= signR_d1;
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shiftedFracY_d1 <= shiftedFracY;
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extendedExpInc_d1 <= extendedExpInc;
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end
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end
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// Exponent difference and swap --
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assign excExpFracX = {X[33:32],X[30:0]};
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assign excExpFracY = {Y[33:32],Y[30:0]};
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assign eXmeY = ({1'b 0,X[30:23]}) - ({1'b 0,Y[30:23]});
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assign eYmeX = ({1'b 0,Y[30:23]}) - ({1'b 0,X[30:23]});
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assign swap = excExpFracX >= excExpFracY ? 1'b 0 : 1'b 1;
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assign newX = swap == 1'b0 ? X : Y;
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assign newY = swap == 1'b0 ? Y : X;
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assign expX = newX[30:23];
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assign excX = newX[33:32];
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assign excY = newY[33:32];
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assign signX = newX[31];
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assign signY = newY[31];
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assign EffSub = signX ^ signY;
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assign sdsXsYExnXY = {signX,signY,excX,excY};
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assign sdExnXY = {excX,excY};
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assign fracY = excY == 2'b00 ? 24'b000000000000000000000000 : {1'b1,newY[22:0]};
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always @(*) begin
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case(sdsXsYExnXY)
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6'b000000,6'b010000,6'b100000,6'b110000 : excRt <= 2'b00;
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6'b000101,6'b010101,6'b100101,6'b110101,6'b000100,6'b010100,6'b100100,6'b110100,6'b000001,6'b010001,6'b100001,6'b110001 : excRt <= 2'b01;
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6'b111010,6'b001010,6'b001000,6'b011000,6'b101000,6'b111000,6'b000010,6'b010010,6'b100010,6'b110010,6'b001001,6'b011001,6'b101001,6'b111001,6'b000110,6'b010110,6'b100110,6'b110110 : excRt <= 2'b10;
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default : excRt <= 2'b 11;
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endcase
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end
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assign signR = (sdsXsYExnXY == 6'b100000 || sdsXsYExnXY == 6'b010000) ? 1'b0 : signX;
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//-------------- cycle 0----------------
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assign expDiff = swap == 1'b0 ? eXmeY : eYmeX;
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assign shiftedOut = (expDiff >= 25) ? 1'b1 : 1'b0;
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assign shiftVal = shiftedOut == 1'b0 ? expDiff[4:0] : 5'b11010;
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FPAdder_8_23_uid2_RightShifter_l2 RightShifterComponent(
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.R(shiftedFracY),
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.S(shiftVal),
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.X(fracY));
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//--------------Synchro barrier, entering cycle 1----------------
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assign sticky = (shiftedFracY_d1[23:0] == 23'b00000000000000000000000) ? 1'b0 : 1'b1;
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//-------------- cycle 0----------------
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//--------------Synchro barrier, entering cycle 1----------------
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assign fracYfar = {1'b 0,shiftedFracY_d1[49:24]};
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assign fracYfarXorOp = fracYfar ^ ({EffSub_d1,EffSub_d1,EffSub_d1,EffSub_d1,EffSub_d1,EffSub_d1,EffSub_d1,EffSub_d1,EffSub_d1,EffSub_d1,EffSub_d1,EffSub_d1,EffSub_d1,EffSub_d1,EffSub_d1,EffSub_d1,EffSub_d1,EffSub_d1,EffSub_d1,EffSub_d1,EffSub_d1,EffSub_d1,EffSub_d1,EffSub_d1,EffSub_d1,EffSub_d1,EffSub_d1});
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assign fracXfar = {2'b01,(newX_d1[22:0]),2'b00};
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assign cInAddFar = EffSub_d1 & ~sticky;
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IntAdder_27_f110_uid6_l2 fracAdder(
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.Cin(cInAddFar),
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.R(fracAddResult),
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.X(fracXfar),
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.Y(fracYfarXorOp));
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assign fracGRS = {fracAddResult,sticky};
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assign extendedExpInc = ({2'b00,expX_d1}) + 1'b1;
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LZCShifter_28_to_28_counting_32_uid16_l2 LZC_component(
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.clk(clk),
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.stall(seq_stall),
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.Count(nZerosNew),
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.I(fracGRS),
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.O(shiftedFrac));
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//--------------Synchro barrier, entering cycle 2----------------
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assign updatedExp = extendedExpInc_d1 - ({5'b00000,nZerosNew});
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assign eqdiffsign = nZerosNew == 5'b11111 ? 1'b1 : 1'b0;
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assign expFrac = {updatedExp,shiftedFrac[26:3]};
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//-------------- cycle 2----------------
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assign stk = shiftedFrac[1] | shiftedFrac[0];
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assign rnd = shiftedFrac[2];
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assign grd = shiftedFrac[3];
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assign lsb = shiftedFrac[4];
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assign addToRoundBit = (lsb == 1'b0 && grd == 1'b1 && rnd == 1'b0 && stk == 1'b0) ? 1'b0 : 1'b1;
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IntAdder_34_f110_uid18_l2 roundingAdder(
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.Cin(addToRoundBit),
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.R(RoundedExpFrac),
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.X(expFrac),
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.Y(34'b0000000000000000000000000000000000));
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//-------------- cycle 2----------------
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assign upExc = RoundedExpFrac[33:32];
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assign fracR = RoundedExpFrac[23:1];
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assign expR = RoundedExpFrac[31:24];
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assign exExpExc = {upExc,excRt_d2};
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always @(*) begin
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case((exExpExc))
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4'b0000,4'b0100,4'b1000,4'b1100,4'b1001,4'b1101 : excRt2 <= 2'b00;
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4'b0001 : excRt2 <= 2'b01;
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4'b0010,4'b0110,4'b0101 : excRt2 <= 2'b10;
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default : excRt2 <= 2'b11;
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endcase
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end
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assign excR = (eqdiffsign == 1'b1 && EffSub_d2 == 1'b1) ? 2'b00 : excRt2;
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assign computedR = {excR,signR_d2,expR,fracR};
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assign R = computedR;
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endmodule
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