74 lines
2.2 KiB
Systemverilog
74 lines
2.2 KiB
Systemverilog
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/*
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* Copyright 2019 - 2020 Systems Group, ETH Zurich
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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module Data_Memory #(
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parameter DATA_WIDTH = 32,
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parameter ADDR_WIDTH = 8
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) (
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input wire clk,
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input wire rst_n,
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input wire we,
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input wire re,
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input wire [ADDR_WIDTH-1:0] raddr,
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input wire [ADDR_WIDTH-2:0] waddr,
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input wire [DATA_WIDTH-1:0] din,
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output reg [31:0] dout,
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output reg valid_out
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);
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wire [DATA_WIDTH-1:0] dline;
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reg raddr_d1;
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reg re_d1;
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dual_port_mem Dualport_mem_inst (
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.clk ( clk ),
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.da ( din ),
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.wea ( we),
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.ena ( we),
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.addra ( waddr ),
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.web (1'b0),
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.addrb ( raddr[ADDR_WIDTH-1:1] ),
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.enb ( re ),
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.qb ( dline )
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);
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always @(posedge clk) begin
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raddr_d1 <= raddr[0];
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re_d1 <= re;
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dout <= (raddr_d1)? dline[63:32] : dline[31:0];
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if(~rst_n) begin
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valid_out <= 1'b0;
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end
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else begin
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valid_out <= re_d1;
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end
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end
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endmodule
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