65 lines
1.5 KiB
VHDL
65 lines
1.5 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity pipe_reg is
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port(
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clk : in std_logic;
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reset_n : in std_logic;
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stall : in std_logic;
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last_in : in std_logic;
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last_out : out std_logic;
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keep_in : in std_logic_vector(15 downto 0);
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keep_out : out std_logic_vector(15 downto 0);
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id_in : in std_logic_vector(5 downto 0);
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id_out : out std_logic_vector(5 downto 0);
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dVal_in : in std_logic; -- Data valid signal
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dVal_out : out std_logic;
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data_in : in std_logic_vector(127 downto 0);
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data_out : out std_logic_vector(127 downto 0)
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);
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end entity pipe_reg;
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architecture RTL of pipe_reg is
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-- Internal registers
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signal dVal_reg : std_logic;
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signal last_reg : std_logic;
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signal keep_reg : std_logic_vector(15 downto 0);
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signal id_reg : std_logic_vector(5 downto 0);
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signal data_reg : std_logic_vector(127 downto 0);
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begin
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-- Register process
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--
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CR_REG: process (clk, reset_n) is
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begin
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if reset_n = '0' then
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dVal_reg <= '0';
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last_reg <= '0';
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keep_reg <= (others => '0');
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id_reg <= (others => '0');
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data_reg <= (others => '0');
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elsif rising_edge(clk) then
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if stall = '0' then
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dVal_reg <= '0';
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if dVal_in = '1' then
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dVal_reg <= '1';
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last_reg <= last_in;
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keep_reg <= keep_in;
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id_reg <= id_in;
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data_reg <= data_in;
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end if;
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end if;
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end if;
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end process CR_REG;
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-- Output
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dVal_out <= dVal_reg;
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last_out <= last_reg;
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keep_out <= keep_reg;
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id_out <= id_reg;
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data_out <= data_reg;
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end architecture RTL; |