64 lines
1.7 KiB
VHDL
64 lines
1.7 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity key_pipeline is
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port(
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clk : in std_logic;
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reset_n : in std_logic;
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keyVal_in : in std_logic; -- Key valid
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keyVal_out : out std_logic;
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key_in : in std_logic_vector(127 downto 0);
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key_out : out std_logic_vector(11*128-1 downto 0)
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);
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end entity key_pipeline;
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architecture RTL of key_pipeline is
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-- Internal signals
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type keyVal_array is array (10 downto 0) of std_logic;
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type key_array is array (10 downto 0) of std_logic_vector(127 downto 0);
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signal keyVal_pipe : keyVal_array; -- Key valid signal pipeline
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signal key_pipe : key_array; -- Key pipeline
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-- Internal RAM for round constants
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type ram_type is array(natural range<>) of std_logic_vector(7 downto 0);
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constant rcon: ram_type(0 to 9) := (X"01", X"02", X"04", X"08", X"10", X"20", X"40", X"80", X"1b", X"36");
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begin
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-- Instantiate base key register
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GEN_KEY_BASE: entity work.key_pipe_reg
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port map(
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clk => clk,
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reset_n => reset_n,
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dVal_in => keyVal_in,
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dVal_out => keyVal_pipe(0),
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data_in => key_in,
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data_out => key_pipe(0)
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);
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-- Instantiate key expansion pipeline
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GEN_KEY_EXP: for i in 0 to 9 generate
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KEY_X: entity work.key_pipe_stage
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port map(
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clk => clk,
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reset_n => reset_n,
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keyVal_in => keyVal_pipe(i),
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keyVal_out => keyVal_pipe(i+1),
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key_in => key_pipe(i),
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key_out => key_pipe(i+1),
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rnd_const => rcon(i)
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);
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end generate GEN_KEY_EXP;
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-- Key valid out
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keyVal_out <= keyVal_pipe(10);
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-- Keys out
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GEN_KEYS_OUT: for i in 0 to 10 generate
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key_out(i*128+127 downto i*128) <= key_pipe(i);
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end generate GEN_KEYS_OUT;
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end architecture RTL; |