55 lines
1.4 KiB
VHDL
55 lines
1.4 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity key_expansion is
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port(
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key_in : in std_logic_vector(127 downto 0);
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key_out : out std_logic_vector(127 downto 0);
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rnd_const : in std_logic_vector(7 downto 0)
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);
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end entity key_expansion;
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architecture RTL of key_expansion is
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-- Internal signals
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type word_array is array (3 downto 0) of std_logic_vector(31 downto 0);
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signal key_word : word_array;
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signal key_next : word_array;
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signal key_shift : std_logic_vector(31 downto 0);
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signal key_s_box : std_logic_vector(31 downto 0);
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signal temp : std_logic_vector(31 downto 0);
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begin
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-- Key words
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GEN_KW: for i in 0 to 3 generate
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key_word(3-i) <= key_in(32*i+31 downto 32*i);
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end generate GEN_KW;
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-- Rotate 8 bits
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key_shift <= key_word(3)(23 downto 0) & key_word(3)(31 downto 24);
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-- S-box
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GEN_SBOX: for i in 0 to 3 generate
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SBOX: entity work.s_box_lut port map(
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data_in => key_shift(i*8+7 downto i*8),
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data_out => key_s_box(i*8+7 downto i*8)
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);
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end generate GEN_SBOX;
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-- Add round constant
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temp(31 downto 24) <= key_s_box(31 downto 24) xor rnd_const;
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temp(23 downto 0) <= key_s_box(23 downto 0);
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-- Next key
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key_next(0) <= key_word(0) xor temp;
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key_next(1) <= key_word(1) xor key_next(0);
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key_next(2) <= key_word(2) xor key_next(1);
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key_next(3) <= key_word(3) xor key_next(2);
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-- Output
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key_out <= key_next(0) & key_next(1) & key_next(2) & key_next(3);
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end architecture RTL;
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