111 lines
2.6 KiB
VHDL
111 lines
2.6 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity aes_top is
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generic(
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NPAR : integer := 2
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);
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port(
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clk : in std_logic;
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reset_n : in std_logic;
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stall : in std_logic;
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-- Key
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key_in : in std_logic_vector(127 downto 0);
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keyVal_in : in std_logic;
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keyVal_out : out std_logic;
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last_in : in std_logic;
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last_out : out std_logic;
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keep_in : in std_logic_vector(NPAR*16-1 downto 0);
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keep_out : out std_logic_vector(NPAR*16-1 downto 0);
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id_in : in std_logic_vector(NPAR*6-1 downto 0);
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id_out : out std_logic_vector(NPAR*6-1 downto 0);
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-- Data valid
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dVal_in : in std_logic; -- Data valid
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dVal_out : out std_logic;
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-- Data
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data_in : in std_logic_vector(NPAR*128-1 downto 0);
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data_out : out std_logic_vector(NPAR*128-1 downto 0)
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);
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end entity aes_top;
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architecture RTL of aes_top is
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type keep_array is array (NPAR-1 downto 0) of std_logic_vector(15 downto 0);
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type id_array is array (NPAR-1 downto 0) of std_logic_vector(5 downto 0);
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-- Internal signals
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signal key_exp : std_logic_vector(11*128-1 downto 0);
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signal dVal : std_logic_vector(NPAR-1 downto 0);
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signal last : std_logic_vector(NPAR-1 downto 0);
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signal keep : keep_array;
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signal id: id_array;
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begin
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-- Instantiate key pipeline
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GEN_KEY_PIPE: entity work.key_pipeline
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port map(
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clk => clk,
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reset_n => reset_n,
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keyVal_in => keyVal_in,
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keyVal_out => keyVal_out,
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key_in => key_in,
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key_out => key_exp
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);
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-- Instantiate AES pipelines
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GEN_AES_PAR: for i in 0 to NPAR-1 generate
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GEN_AES_PIPE: entity work.aes_pipeline
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port map(
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clk => clk,
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reset_n => reset_n,
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stall => stall,
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-- Key
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key_in => key_exp,
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-- Data valid
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dVal_in => dVal_in,
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dVal_out => dVal(i),
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last_in => last_in,
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last_out => last(i),
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keep_in => keep_in(i*16+15 downto i*16),
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keep_out => keep(i),
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id_in => id_in(i*6+5 downto i*6),
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id_out => id(i),
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-- Data
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data_in => data_in(i*128+127 downto i*128),
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data_out => data_out(i*128+127 downto i*128)
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);
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end generate GEN_AES_PAR;
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GEN_VALID: process (dVal) is
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variable tmp : std_logic;
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begin
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tmp := '0';
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for i in 0 to NPAR-1 loop
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tmp := tmp or dVal(i);
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end loop;
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dVal_out <= tmp;
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end process GEN_VALID;
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GEN_LAST: process (last) is
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variable tmp : std_logic;
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begin
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tmp := '0';
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for i in 0 to NPAR-1 loop
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tmp := tmp or last(i);
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end loop;
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last_out <= tmp;
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end process GEN_LAST;
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GEN_KEEP: for i in 0 to NPAR-1 generate
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keep_out(i*16+15 downto i*16) <= keep(i);
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end generate GEN_KEEP;
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GEN_ID: for i in 0 to NPAR-1 generate
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id_out(i*6+5 downto i*6) <= id(i);
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end generate GEN_ID;
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end architecture RTL; |