267 lines
6.5 KiB
Systemverilog
267 lines
6.5 KiB
Systemverilog
import lynxTypes::*;
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module aes_slave (
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input logic aclk,
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input logic aresetn,
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AXI4L.s axi_ctrl,
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output logic [127:0] key_out,
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output logic keyStart,
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output logic [127:0] iv_out,
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output logic [3:0] ivDest,
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output logic ivStart
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);
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//`define DEBUG_CNFG_SLAVE
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// -- Decl ----------------------------------------------------------
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// ------------------------------------------------------------------
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// Constants
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localparam integer N_REGS = 5;
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localparam integer ADDR_LSB = $clog2(AXIL_DATA_BITS/8);
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localparam integer ADDR_MSB = $clog2(N_REGS);
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localparam integer AXI_ADDR_BITS = ADDR_LSB + ADDR_MSB;
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// Internal registers
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logic [AXI_ADDR_BITS-1:0] axi_awaddr;
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logic axi_awready;
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logic [AXI_ADDR_BITS-1:0] axi_araddr;
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logic axi_arready;
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logic [1:0] axi_bresp;
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logic axi_bvalid;
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logic axi_wready;
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logic [AXIL_DATA_BITS-1:0] axi_rdata;
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logic [1:0] axi_rresp;
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logic axi_rvalid;
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// Registers
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logic [N_REGS-1:0][AXIL_DATA_BITS-1:0] slv_reg;
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logic slv_reg_rden;
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logic slv_reg_wren;
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logic aw_en;
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// -- Def -----------------------------------------------------------
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// ------------------------------------------------------------------
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// -- Register map -----------------------------------------------------------------------
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localparam integer KEY_LOW_REG = 0;
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localparam integer KEY_HIGH_REG = 1;
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localparam integer IV_DEST_REG = 2;
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localparam integer IV_LOW_REG = 3;
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localparam integer IV_HIGH_REG = 4;
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// Write process
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assign slv_reg_wren = axi_wready && axi_ctrl.wvalid && axi_awready && axi_ctrl.awvalid;
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always_ff @(posedge aclk) begin
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if ( aresetn == 1'b0 ) begin
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slv_reg <= 0;
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keyStart <= 1'b0;
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ivStart <= 1'b0;
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end
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else begin
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keyStart <= 1'b0;
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ivStart <= 1'b0;
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if(slv_reg_wren) begin
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case (axi_awaddr[ADDR_LSB+:ADDR_MSB])
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KEY_LOW_REG:
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for (int i = 0; i < (AXIL_DATA_BITS/8); i++) begin
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if(axi_ctrl.wstrb[i]) begin
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slv_reg[KEY_LOW_REG][(i*8)+:8] <= axi_ctrl.wdata[(i*8)+:8];
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end
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end
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KEY_HIGH_REG:
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for (int i = 0; i < (AXIL_DATA_BITS/8); i++) begin
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if(axi_ctrl.wstrb[i]) begin
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slv_reg[KEY_HIGH_REG][(i*8)+:8] <= axi_ctrl.wdata[(i*8)+:8];
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keyStart <= 1'b1;
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end
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end
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IV_DEST_REG:
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for (int i = 0; i < (AXIL_DATA_BITS/8); i++) begin
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if(axi_ctrl.wstrb[i]) begin
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slv_reg[IV_DEST_REG][(i*8)+:8] <= axi_ctrl.wdata[(i*8)+:8];
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end
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end
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IV_LOW_REG:
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for (int i = 0; i < (AXIL_DATA_BITS/8); i++) begin
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if(axi_ctrl.wstrb[i]) begin
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slv_reg[IV_LOW_REG][(i*8)+:8] <= axi_ctrl.wdata[(i*8)+:8];
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end
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end
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IV_HIGH_REG:
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for (int i = 0; i < (AXIL_DATA_BITS/8); i++) begin
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if(axi_ctrl.wstrb[i]) begin
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slv_reg[IV_HIGH_REG][(i*8)+:8] <= axi_ctrl.wdata[(i*8)+:8];
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ivStart <= 1'b1;
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end
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end
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default : ;
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endcase
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end
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end
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end
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assign key_out[63:0] = slv_reg[KEY_LOW_REG];
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assign key_out[127:64] = slv_reg[KEY_HIGH_REG];
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assign ivDest = slv_reg[IV_DEST_REG][3:0];
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assign iv_out[63:0] = slv_reg[IV_LOW_REG];
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assign iv_out[127:64] = slv_reg[IV_HIGH_REG];
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// Read process
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assign slv_reg_rden = axi_arready & axi_ctrl.arvalid & ~axi_rvalid;
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always_ff @(posedge aclk) begin
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if( aresetn == 1'b0 ) begin
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axi_rdata <= 0;
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end
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else begin
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if(slv_reg_rden) begin
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axi_rdata <= 0;
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case (axi_araddr[ADDR_LSB+:ADDR_MSB])
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KEY_LOW_REG:
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axi_rdata <= slv_reg[KEY_LOW_REG];
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KEY_HIGH_REG:
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axi_rdata <= slv_reg[KEY_HIGH_REG];
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IV_DEST_REG:
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axi_rdata <= slv_reg[IV_DEST_REG];
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IV_LOW_REG:
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axi_rdata <= slv_reg[IV_LOW_REG];
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IV_HIGH_REG:
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axi_rdata <= slv_reg[IV_HIGH_REG];
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default: ;
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endcase
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end
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end
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end
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// I/O
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assign axi_ctrl.awready = axi_awready;
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assign axi_ctrl.arready = axi_arready;
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assign axi_ctrl.bresp = axi_bresp;
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assign axi_ctrl.bvalid = axi_bvalid;
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assign axi_ctrl.wready = axi_wready;
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assign axi_ctrl.rdata = axi_rdata;
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assign axi_ctrl.rresp = axi_rresp;
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assign axi_ctrl.rvalid = axi_rvalid;
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// awready and awaddr
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always_ff @(posedge aclk) begin
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if ( aresetn == 1'b0 )
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begin
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axi_awready <= 1'b0;
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axi_awaddr <= 0;
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aw_en <= 1'b1;
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end
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else
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begin
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if (~axi_awready && axi_ctrl.awvalid && axi_ctrl.wvalid && aw_en)
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begin
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axi_awready <= 1'b1;
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aw_en <= 1'b0;
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axi_awaddr <= axi_ctrl.awaddr;
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end
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else if (axi_ctrl.bready && axi_bvalid)
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begin
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aw_en <= 1'b1;
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axi_awready <= 1'b0;
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end
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else
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begin
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axi_awready <= 1'b0;
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end
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end
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end
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// arready and araddr
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always_ff @(posedge aclk) begin
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if ( aresetn == 1'b0 )
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begin
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axi_arready <= 1'b0;
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axi_araddr <= 0;
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end
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else
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begin
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if (~axi_arready && axi_ctrl.arvalid)
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begin
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axi_arready <= 1'b1;
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axi_araddr <= axi_ctrl.araddr;
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end
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else
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begin
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axi_arready <= 1'b0;
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end
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end
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end
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// bvalid and bresp
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always_ff @(posedge aclk) begin
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if ( aresetn == 1'b0 )
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begin
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axi_bvalid <= 0;
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axi_bresp <= 2'b0;
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end
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else
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begin
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if (axi_awready && axi_ctrl.awvalid && ~axi_bvalid && axi_wready && axi_ctrl.wvalid)
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begin
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axi_bvalid <= 1'b1;
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axi_bresp <= 2'b0;
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end
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else
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begin
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if (axi_ctrl.bready && axi_bvalid)
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begin
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axi_bvalid <= 1'b0;
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end
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end
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end
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end
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// wready
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always_ff @(posedge aclk) begin
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if ( aresetn == 1'b0 )
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begin
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axi_wready <= 1'b0;
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end
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else
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begin
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if (~axi_wready && axi_ctrl.wvalid && axi_ctrl.awvalid && aw_en )
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begin
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axi_wready <= 1'b1;
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end
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else
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begin
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axi_wready <= 1'b0;
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end
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end
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end
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// rvalid and rresp (1Del?)
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always_ff @(posedge aclk) begin
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if ( aresetn == 1'b0 )
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begin
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axi_rvalid <= 0;
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axi_rresp <= 0;
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end
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else
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begin
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if (axi_arready && axi_ctrl.arvalid && ~axi_rvalid)
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begin
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axi_rvalid <= 1'b1;
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axi_rresp <= 2'b0;
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end
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else if (axi_rvalid && axi_ctrl.rready)
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begin
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axi_rvalid <= 1'b0;
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end
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end
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end
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endmodule // cnfg_slave
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