43 lines
1.0 KiB
VHDL
43 lines
1.0 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity aes_round_last is
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port(
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key_in : in std_logic_vector(127 downto 0);
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key_last : in std_logic_vector(127 downto 0);
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data_in : in std_logic_vector(127 downto 0);
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data_out : out std_logic_vector(127 downto 0)
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);
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end entity aes_round_last;
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architecture RTL of aes_round_last is
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-- Internal signals
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signal data_in_sbox : std_logic_vector(127 downto 0);
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signal data_out_sbox : std_logic_vector(127 downto 0);
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signal data_out_sr : std_logic_vector(127 downto 0);
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begin
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-- Add round key
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data_in_sbox <= data_in xor key_in;
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-- S-box stage
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GEN_SBOX: for i in 0 to 15 generate
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SBOX: entity work.s_box_lut port map(
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data_in => data_in_sbox(8*i+7 downto 8*i),
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data_out => data_out_sbox(8*i+7 downto 8*i)
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);
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end generate GEN_SBOX;
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-- Shift row
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GEN_SROW: entity work.shift_rows port map(
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data_in => data_out_sbox,
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data_out => data_out_sr
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);
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-- Last add round key
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data_out <= data_out_sr xor key_last;
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end architecture RTL; |