109 lines
2.8 KiB
VHDL
109 lines
2.8 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity aes_pipeline is
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port(
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clk : in std_logic;
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reset_n : in std_logic;
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stall : in std_logic;
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-- Key
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key_in : in std_logic_vector(11*128-1 downto 0);
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last_in : in std_logic;
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last_out : out std_logic;
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keep_in : in std_logic_vector(15 downto 0);
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keep_out : out std_logic_vector(15 downto 0);
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id_in : in std_logic_vector(5 downto 0);
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id_out : out std_logic_vector(5 downto 0);
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-- Data valid
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dVal_in : in std_logic; -- Data valid
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dVal_out : out std_logic;
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-- Data
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data_in : in std_logic_vector(127 downto 0);
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data_out : out std_logic_vector(127 downto 0)
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);
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end entity aes_pipeline;
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architecture RTL of aes_pipeline is
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-- Internal signals
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type dVal_array is array (8 downto 0) of std_logic;
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type data_array is array (8 downto 0) of std_logic_vector(127 downto 0);
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type last_array is array (8 downto 0) of std_logic;
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type keep_array is array (8 downto 0) of std_logic_vector(15 downto 0);
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type id_array is array (8 downto 0) of std_logic_vector(5 downto 0);
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signal dVal_pipe : dVal_array; -- Data valid signal pipeline
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signal data_pipe : data_array; -- Data pipeline
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signal last_pipe : last_array;
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signal keep_pipe : keep_array;
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signal id_pipe : id_array;
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begin
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-- Instantiate regular AES stages
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GEN_AES: for i in 0 to 8 generate
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GEN_S0: if i = 0 generate
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S0: entity work.aes_pipe_stage
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port map(
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clk => clk,
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reset_n => reset_n,
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stall => stall,
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key_in => key_in(127 downto 0),
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last_in => last_in,
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last_out => last_pipe(0),
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keep_in => keep_in,
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keep_out => keep_pipe(0),
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id_in => id_in,
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id_out => id_pipe(0),
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dVal_in => dVal_in,
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dVal_out => dVal_pipe(0),
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data_in => data_in,
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data_out => data_pipe(0)
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);
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end generate GEN_S0;
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GEN_SX: if i > 0 generate
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SX: entity work.aes_pipe_stage
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port map(
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clk => clk,
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reset_n => reset_n,
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stall => stall,
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key_in => key_in(128*i+127 downto 128*i),
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last_in => last_pipe(i-1),
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last_out => last_pipe(i),
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keep_in => keep_pipe(i-1),
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keep_out => keep_pipe(i),
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id_in => id_pipe(i-1),
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id_out => id_pipe(i),
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dVal_in => dVal_pipe(i-1),
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dVal_out => dVal_pipe(i),
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data_in => data_pipe(i-1),
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data_out => data_pipe(i)
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);
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end generate GEN_SX;
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end generate GEN_AES;
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-- Instantiate last stage
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SL: entity work.aes_pipe_stage_last
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port map(
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clk => clk,
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reset_n => reset_n,
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stall => stall,
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key_in => key_in(128*9+127 downto 128*9),
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key_last => key_in(128*10+127 downto 128*10),
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last_in => last_pipe(8),
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last_out => last_out,
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keep_in => keep_pipe(8),
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keep_out => keep_out,
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id_in => id_pipe(8),
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id_out => id_out,
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dVal_in => dVal_pipe(8),
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dVal_out => dVal_out,
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data_in => data_pipe(8),
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data_out => data_out
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);
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end architecture RTL; |