172 lines
5.5 KiB
C
172 lines
5.5 KiB
C
/**
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* Copyright (c) 2023, Systems Group, ETH Zurich
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of the copyright holder nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __HYPERVISOR_H__
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#define __HYPERVISOR_H__
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#include "../coyote_dev.h"
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#include <linux/eventfd.h>
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// #define HYPERVISOR_TEST
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#define NUM_INTERRUPTS 1
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#define MAX_VMS 16
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#define COYOTE_HYPERVISOR_CONFIG_SIZE 0x100
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#define COYOTE_HYPERVISOR_BAR0_SIZE ((uint64_t)FPGA_CTRL_SIZE)
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#define COYOTE_HYPERVISOR_BAR2_SIZE ((uint64_t)0x4000)
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#define COYOTE_HYPERVISOR_BAR4_SIZE ((uint64_t)FPGA_CTRL_CNFG_AVX_SIZE)
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#define COYOTE_HYPERVISOR_BAR0_MASK ~(COYOTE_HYPERVISOR_BAR0_SIZE - 1)
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#define COYOTE_HYPERVISOR_BAR2_MASK ~(COYOTE_HYPERVISOR_BAR2_SIZE - 1)
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#define COYOTE_HYPERVISOR_BAR4_MASK ~(COYOTE_HYPERVISOR_BAR4_SIZE - 1)
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#define COYOTE_HYPERVISOR_PCI_MASK(__size) (~(__size - 1))
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#define BAR0_INDEX_SHIFT 16
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#define COYOTE_REGION_OFFSET 32
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#define COYOTE_GET_INDEX(__addr) (__addr >> COYOTE_REGION_OFFSET)
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#define COYOTE_INDEX_TO_ADDR(__index) (__index << COYOTE_REGION_OFFSET);
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#define HYPERVISOR_OFFSET_MASK (((uint64_t)1 << COYOTE_REGION_OFFSET) - 1)
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/* Offsets into BAR2 */
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#define REGISTER_PID_OFFSET 0x00
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#define UNREGISTER_PID_OFFSET 0x08
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#define MAP_USER_OFFSET 0x10
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#define UNMAP_USER_OFFSET 0x18
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#define READ_CNFG_OFFSET 0x20
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#define PUT_ALL_USER_PAGES 0x28
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#define TEST_INTERRUPT_OFFSET 0x30
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#define INVALID_CPID 0xffffffffffffffff
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#define HYPERVISOR_HASH_TABLE_ORDER 8
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#define HASH_TABLE_BUCKETS (1 << HYPERVISOR_HASH_TABLE_ORDER)
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#define MAX_USER_BUF_SHIFT 27
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#define MAX_USER_BUF_SIZE (1 << MAX_USER_BUF_SHIFT)
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#define LARGE_TABLE_SHIFT 21
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#define LARGE_TABLE_SIZE (1 << 21)
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#define MSIX_OFFSET 0x40
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#define MSIX_SIZE sizeof(struct msix_cap_header)
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/* PCI-Capability header */
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struct cap_header
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{
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uint8_t cap_id;
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uint8_t next_pointer;
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} __packed;
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/* MSI-X header*/
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struct msix_cap_header
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{
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uint8_t cap_id;
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uint8_t next_pointer;
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uint16_t message_control;
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uint32_t table_offset;
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uint32_t pba_offset;
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uint32_t mua;
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} __packed;
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// struct to manage information about a single entry of an interrupt vector
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struct msix_interrupt
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{
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int eventfd;
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struct eventfd_ctx * ctx;
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int masked;
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};
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/* PCI config header */
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struct pci_config_space
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{
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uint16_t vendor_id; // 0x00 RO
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uint16_t device_id; // 0x02 RO
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uint16_t command; // 0x04
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uint16_t status; // 0x06
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uint8_t revison_id; // 0x08 RO
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uint8_t programming_interface; // 0x09
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uint8_t subclass; // 0x0a
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uint8_t class_code; // 0x0b RO
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uint8_t cache_line_size; // 0x0c
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uint8_t lat_time; // 0x0d
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uint8_t header_typer; // 0x0e RO
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uint8_t bist; // 0x0f
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uint32_t bar0; // 0x10
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uint32_t bar1; // 0x14
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uint32_t bar2; // 0x18
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uint32_t bar3; // 0x1c
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uint32_t bar4; // 0x20
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uint32_t bar5; // 0x24
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uint32_t cardbus_pointer; // 0x28
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uint16_t subsys_vendor_id; // 0x2c
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uint16_t subsys_id; // 0x2e
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uint32_t expansion_rom_base; // 0x30
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uint8_t cap_pointer; // 0x34
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uint8_t reserved[7]; // 0x35
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uint8_t interrupt_line; // 0x3c
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uint8_t interrupt_pin; // 0x3d
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uint8_t min_gnt; // 0x3e
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uint8_t max_lat; // 0x3f
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uint8_t cap_section[0xbf]; // 0x40
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} __packed;
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struct hypervisor_map_notifier
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{
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uint64_t npages;
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uint64_t len;
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uint64_t gva;
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uint64_t cpid;
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uint64_t dirtied;
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uint64_t is_huge;
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uint64_t gpas[0];
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};
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/* Mediated vFPGA management data */
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struct m_fpga_dev
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{
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struct fpga_dev *fpga; // Parent fpga struct
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uint32_t id;
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struct list_head next; // next virtual fpga
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struct pci_config_space pci_config;
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spinlock_t current_cpid_lock;
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uint64_t current_cpid;
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struct kvm *kvm;
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uint32_t in_use;
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struct notifier_block notifier;
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void *msix_table;
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struct msix_interrupt *msix_vector;
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struct hlist_head sbuff_map[HASH_TABLE_BUCKETS];
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spinlock_t lock;
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};
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#endif
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