53 lines
2.3 KiB
C
53 lines
2.3 KiB
C
/**
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* Copyright (c) 2021, Systems Group, ETH Zurich
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of the copyright holder nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __FPGA_PR_H__
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#define __FPGA_PR_H__
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#include "coyote_dev.h"
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/*
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██████╗ ██████╗
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██╔══██╗██╔══██╗
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██████╔╝██████╔╝
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██╔═══╝ ██╔══██╗
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██║ ██║ ██║
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╚═╝ ╚═╝ ╚═╝
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*/
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/* ISR */
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irqreturn_t pr_isr(int irq, void *dev_id);
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/* Mem ops */
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int alloc_pr_buffers(struct pr_dev *d, unsigned long n_pages, pid_t pid, uint32_t crid);
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int free_pr_buffers(struct pr_dev *d, uint64_t vaddr, pid_t pid, uint32_t crid);
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/* Reconfigurations */
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void pr_clear_irq(struct pr_dev *d);
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int reconfigure_start(struct pr_dev *d, uint64_t vaddr, uint64_t len, pid_t pid, uint32_t crid);
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#endif // FPGA PR
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