62 lines
3.1 KiB
C
62 lines
3.1 KiB
C
/**
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* Copyright (c) 2021, Systems Group, ETH Zurich
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of the copyright holder nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __FPGA_GUP_H__
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#define __FPGA_GUP_H__
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#include "coyote_dev.h"
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#include "fpga_hw.h"
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/*
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███╗ ███╗███╗ ███╗██╗ ██╗
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████╗ ████║████╗ ████║██║ ██║
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██╔████╔██║██╔████╔██║██║ ██║
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██║╚██╔╝██║██║╚██╔╝██║██║ ██║
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██║ ╚═╝ ██║██║ ╚═╝ ██║╚██████╔╝
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╚═╝
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*/
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/* MMU */
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int mmu_handler_gup(struct fpga_dev *d, uint64_t vaddr, uint64_t len, int32_t cpid, int32_t stream, pid_t hpid);
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/* Mapping */
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struct user_pages* map_present(struct fpga_dev *d, struct desc_aligned *pfa);
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void tlb_map_gup(struct fpga_dev *d, struct desc_aligned *pfa, struct user_pages *user_pg, pid_t hpid);
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void tlb_unmap_gup(struct fpga_dev *d, struct user_pages *user_pg, pid_t hpid);
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/* PTW */
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struct user_pages* tlb_get_user_pages(struct fpga_dev *d, struct desc_aligned *pfa, pid_t hpid, struct task_struct *curr_task, struct mm_struct *curr_mm);
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int tlb_put_user_pages(struct fpga_dev *d, uint64_t vaddr, int32_t cpid, pid_t hpid, int dirtied);
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int tlb_put_user_pages_cpid(struct fpga_dev *d, int32_t cpid, pid_t hpid, int dirtied);
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/* DMA */
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void migrate_to_card_gup(struct fpga_dev *d, struct user_pages *user_pg);
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void migrate_to_host_gup(struct fpga_dev *d, struct user_pages *user_pg);
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int offload_user_gup(struct fpga_dev *d, uint64_t vaddr, int32_t cpid);
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int sync_user_gup(struct fpga_dev *d, uint64_t vaddr, int32_t cpid);
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#endif /* FPGA GUP */ |