From b6dbad397648610679ee0eccb87919e6e9aaa979 Mon Sep 17 00:00:00 2001 From: kodario Date: Wed, 12 Oct 2022 19:22:55 +0200 Subject: [PATCH] pr timing fix, stripe reorder buff. --- hw/hdl/cdma_common/axi_stripe_rd.sv | 327 ----------------- hw/hdl/cdma_common/axi_stripe_wr.sv | 346 ------------------ hw/hdl/{cdma_common => stripe}/axi_stripe.sv | 56 ++- hw/hdl/stripe/axi_stripe_a.sv | 302 +++++++++++++++ hw/hdl/stripe/axi_stripe_b.sv | 148 ++++++++ hw/hdl/stripe/axi_stripe_r.sv | 171 +++++++++ .../wr_hdl/template_gen/cyt_top_u200.txt | 6 +- .../wr_hdl/template_gen/cyt_top_u250.txt | 6 +- .../wr_hdl/template_gen/cyt_top_u280.txt | 6 +- .../wr_hdl/template_gen/cyt_top_u50.txt | 6 +- .../wr_hdl/template_gen/cyt_top_u55c.txt | 6 +- .../wr_hdl/template_gen/cyt_top_vcu118.txt | 6 +- hw/scripts/wr_hdl/template_gen/lynx_pkg.txt | 3 +- hw/scripts/wr_hdl/template_gen/top_shell.txt | 34 +- 14 files changed, 697 insertions(+), 726 deletions(-) delete mode 100644 hw/hdl/cdma_common/axi_stripe_rd.sv delete mode 100644 hw/hdl/cdma_common/axi_stripe_wr.sv rename hw/hdl/{cdma_common => stripe}/axi_stripe.sv (86%) create mode 100644 hw/hdl/stripe/axi_stripe_a.sv create mode 100644 hw/hdl/stripe/axi_stripe_b.sv create mode 100644 hw/hdl/stripe/axi_stripe_r.sv diff --git a/hw/hdl/cdma_common/axi_stripe_rd.sv b/hw/hdl/cdma_common/axi_stripe_rd.sv deleted file mode 100644 index fd98df7..0000000 --- a/hw/hdl/cdma_common/axi_stripe_rd.sv +++ /dev/null @@ -1,327 +0,0 @@ -/** - * Copyright (c) 2021, Systems Group, ETH Zurich - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -`timescale 1ns / 1ps - -import lynxTypes::*; - -module axi_stripe_rd ( - input logic aclk, - input logic aresetn, - - // AR - input logic[AXI_ADDR_BITS-1:0] s_axi_araddr, - input logic[1:0] s_axi_arburst, - input logic[3:0] s_axi_arcache, - input logic[AXI_ID_BITS-1:0] s_axi_arid, - input logic[7:0] s_axi_arlen, - input logic[0:0] s_axi_arlock, - input logic[2:0] s_axi_arprot, - input logic[3:0] s_axi_arqos, - input logic[3:0] s_axi_arregion, - input logic[2:0] s_axi_arsize, - output logic s_axi_arready, - input logic s_axi_arvalid, - - output logic[AXI_ADDR_BITS-1:0] m_axi_araddr, - output logic[1:0] m_axi_arburst, - output logic[3:0] m_axi_arcache, - output logic[AXI_ID_BITS-1:0] m_axi_arid, - output logic[7:0] m_axi_arlen, - output logic[0:0] m_axi_arlock, - output logic[2:0] m_axi_arprot, - output logic[3:0] m_axi_arqos, - output logic[3:0] m_axi_arregion, - output logic[2:0] m_axi_arsize, - input logic m_axi_arready, - output logic m_axi_arvalid, - - // R - output logic[AXI_DATA_BITS-1:0] s_axi_rdata, - output logic[AXI_ID_BITS-1:0] s_axi_rid, - output logic s_axi_rlast, - output logic[1:0] s_axi_rresp, - input logic s_axi_rready, - output logic s_axi_rvalid, - - input logic[AXI_DATA_BITS-1:0] m_axi_rdata, - input logic[AXI_ID_BITS-1:0] m_axi_rid, - input logic m_axi_rlast, - input logic[1:0] m_axi_rresp, - output logic m_axi_rready, - input logic m_axi_rvalid -); - -`ifdef MULT_DDR_CHAN - -localparam integer N_OUTSTANDING_STRIPE = 8 * N_OUTSTANDING; -localparam integer FRAG_LOG_BITS = $clog2(DDR_FRAG_SIZE); -localparam integer BEAT_LOG_BITS = $clog2(AXI_DATA_BITS/8); - -// FSM -typedef enum logic[0:0] {ST_IDLE, ST_PARSE} state_t; -logic[0:0] state_C, state_N; - -logic [AXI_ADDR_BITS-1:0] araddr_C, araddr_N; -logic [1:0] arburst_C, arburst_N; -logic [3:0] arcache_C, arcache_N; -logic [1:0] arid_C, arid_N; -logic [7:0] arlen_C, arlen_N; -logic [0:0] arlock_C, arlock_N; -logic [2:0] arprot_C, arprot_N; -logic [3:0] arqos_C, arqos_N; -logic [3:0] arregion_C, arregion_N; -logic [2:0] arsize_C, arsize_N; - -logic [AXI_ADDR_BITS-1:0] paddr_C, paddr_N; -logic [7:0] plen_C, plen_N; -logic done_C, done_N; - -logic [7:0] clen; -logic [7:0] slen; - -logic [AXI_ADDR_BITS-1:0] lsb_mask; -assign lsb_mask = (1 << FRAG_LOG_BITS) - 1; -logic [AXI_ADDR_BITS-1:0] chan_mask; -always_comb begin - chan_mask = 0; - chan_mask[FRAG_LOG_BITS+:N_DDR_CHAN_BITS] = ~0; -end -logic [AXI_ADDR_BITS-1:0] msb_mask; -assign msb_mask = (~lsb_mask) << N_DDR_CHAN_BITS; - -// REG -always_ff @(posedge aclk) begin - if(~aresetn) begin - state_C <= ST_IDLE; - - araddr_C <= 'X; - arburst_C <= 'X; - arcache_C <= 'X; - arid_C <= 'X; - arlen_C <= 'X; - arlock_C <= 'X; - arprot_C <= 'X; - arqos_C <= 'X; - arregion_C <= 'X; - arsize_C <= 'X; - - paddr_C <= 'X; - plen_C <= 'X; - done_C <= 1'b0; - end - else begin - state_C <= state_N; - - araddr_C <= araddr_N; - arburst_C <= arburst_N; - arcache_C <= arcache_N; - arid_C <= arid_N; - arlen_C <= arlen_N; - arlock_C <= arlock_N; - arprot_C <= arprot_N; - arqos_C <= arqos_N; - arregion_C <= arregion_N; - arsize_C <= arsize_N; - - paddr_C <= paddr_N; - plen_C <= plen_N; - done_C <= done_N; - end -end - -// NSL -always_comb begin - state_N = state_C; - - case (state_C) - ST_IDLE: - state_N = s_axi_arvalid ? ST_PARSE : ST_IDLE; - - ST_PARSE: - state_N = (done_C & m_axi_arvalid & m_axi_arready) ? ST_IDLE : ST_PARSE; - - endcase -end - -// DP -always_comb begin - araddr_N = araddr_C; - arburst_N = arburst_C; - arcache_N = arcache_C; - arid_N = arid_C; - arlen_N = arlen_C; - arlock_N = arlock_C; - arprot_N = arprot_C; - arqos_N = arqos_C; - arregion_N = arregion_C; - arsize_N = arsize_C; - - paddr_N = paddr_C; - plen_N = plen_C; - done_N = done_C; - - slen = ((DDR_FRAG_SIZE >> BEAT_LOG_BITS) - ((s_axi_araddr & lsb_mask) >> BEAT_LOG_BITS)) - 1; - clen = ((DDR_FRAG_SIZE >> BEAT_LOG_BITS) - ((araddr_C & lsb_mask) >> BEAT_LOG_BITS)) - 1; - - // Sink - s_axi_arready = 1'b0; - - // Src - m_axi_arvalid = 1'b0; - - case (state_C) - ST_IDLE: begin - if(s_axi_arvalid) begin - s_axi_arready = 1'b1; - - araddr_N = s_axi_araddr; - arburst_N = s_axi_arburst; - arcache_N = s_axi_arcache; - arid_N = s_axi_arid; - arlock_N = s_axi_arlock; - arprot_N = s_axi_arprot; - arqos_N = s_axi_arqos; - arregion_N = s_axi_arregion; - arsize_N = s_axi_arsize; - - paddr_N = (s_axi_araddr[FRAG_LOG_BITS+:N_DDR_CHAN_BITS] << DDR_CHAN_SIZE) | (s_axi_araddr & lsb_mask) | ((s_axi_araddr & msb_mask) >> N_DDR_CHAN_BITS); - araddr_N = ((s_axi_araddr >> FRAG_LOG_BITS) << FRAG_LOG_BITS) + DDR_FRAG_SIZE; - if(slen < s_axi_arlen) begin - plen_N = slen; - arlen_N = s_axi_arlen - slen - 1; - done_N = 1'b0; - end - else begin - plen_N = s_axi_arlen; - arlen_N = 0; - done_N = 1'b1; - end - end - end - - ST_PARSE: begin - m_axi_arvalid = 1'b1; - if(m_axi_arready) begin - paddr_N = (araddr_C[FRAG_LOG_BITS+:N_DDR_CHAN_BITS] << DDR_CHAN_SIZE) | (araddr_C & lsb_mask) | ((araddr_C & msb_mask) >> N_DDR_CHAN_BITS); - araddr_N = ((araddr_C >> FRAG_LOG_BITS) << FRAG_LOG_BITS) + DDR_FRAG_SIZE; - if(clen < arlen_C) begin - plen_N = clen; - arlen_N = arlen_C - clen - 1; - done_N = 1'b0; - end - else begin - plen_N = arlen_C; - arlen_N = 0; - done_N = 1'b1; - end - end - end - - endcase -end - -// AR -assign m_axi_araddr = paddr_C; -assign m_axi_arburst = arburst_C; -assign m_axi_arcache = arcache_C; -assign m_axi_arid = arid_C; -assign m_axi_arlen = plen_C; -assign m_axi_arlock = arlock_C; -assign m_axi_arprot = arprot_C; -assign m_axi_arqos = arqos_C; -assign m_axi_arregion = arregion_C; -assign m_axi_arsize = arsize_C; - -metaIntf #(.STYPE(logic)) seq_snk (); -metaIntf #(.STYPE(logic)) seq_src (); - -assign seq_snk.valid = m_axi_arvalid & m_axi_arready; -assign seq_snk.data = done_C; - -// SEQ -queue_meta #(.QDEPTH(N_OUTSTANDING_STRIPE)) inst_seq_que (.aclk(aclk), .aresetn(aresetn), .s_meta(seq_snk), .m_meta(seq_src)); - -// R -assign s_axi_rdata = m_axi_rdata; -assign s_axi_rid = m_axi_arid; -assign s_axi_rlast = seq_src.data; -assign s_axi_rresp = m_axi_rresp; -assign s_axi_rvalid = m_axi_rvalid; -assign m_axi_rready = s_axi_rready; - -assign seq_src.ready = s_axi_rvalid & s_axi_rready; - -/* -ila_rd inst_ila_rd ( - .clk(aclk), - .probe0(araddr_C[39:0]), // 40 - .probe1(arlen_C), // 8 - .probe2(paddr_C[39:0]), // 40 - .probe3(plen_C), // 8 - .probe4(slen), // 8 - .probe5(clen), // 8 - .probe6(state_C), - .probe7(s_axi_araddr[39:0]), // 40 - .probe8(s_axi_arlen), // 8 - .probe9(s_axi_arvalid), - .probe10(s_axi_arready), - .probe11(m_axi_araddr[39:0]), // 40 - .probe12(m_axi_arlen), // 8 - .probe13(m_axi_arvalid), - .probe14(m_axi_arready), - .probe15(s_axi_rvalid), - .probe16(s_axi_rready), - .probe17(s_axi_rlast), - .probe18(s_axi_rdata) // 512 -); -*/ - -`else - -assign m_axi_araddr = s_axi_araddr; -assign m_axi_arburst = s_axi_arburst; -assign m_axi_arcache = s_axi_arcache; -assign m_axi_arid = s_axi_arid; -assign m_axi_arlen = s_axi_arlen; -assign m_axi_arlock = s_axi_arlock; -assign m_axi_arprot = s_axi_arprot; -assign m_axi_arqos = s_axi_arqos; -assign m_axi_arregion = s_axi_arregion; -assign m_axi_arsize = s_axi_arsize; -assign m_axi_arvalid = s_axi_arvalid; -assign s_axi_arready = m_axi_arready; -assign s_axi_rdata = m_axi_rdata; -assign s_axi_rid = m_axi_rid; -assign s_axi_rlast = m_axi_rlast; -assign s_axi_rresp = m_axi_rresp; -assign m_axi_rready = s_axi_rready; -assign s_axi_rvalid = m_axi_rvalid; - -`endif - -endmodule \ No newline at end of file diff --git a/hw/hdl/cdma_common/axi_stripe_wr.sv b/hw/hdl/cdma_common/axi_stripe_wr.sv deleted file mode 100644 index 78ef788..0000000 --- a/hw/hdl/cdma_common/axi_stripe_wr.sv +++ /dev/null @@ -1,346 +0,0 @@ -/** - * Copyright (c) 2021, Systems Group, ETH Zurich - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -`timescale 1ns / 1ps - -import lynxTypes::*; - -module axi_stripe_wr ( - input logic aclk, - input logic aresetn, - - // AW - input logic[AXI_ADDR_BITS-1:0] s_axi_awaddr, - input logic[1:0] s_axi_awburst, - input logic[3:0] s_axi_awcache, - input logic[AXI_ID_BITS-1:0] s_axi_awid, - input logic[7:0] s_axi_awlen, - input logic[0:0] s_axi_awlock, - input logic[2:0] s_axi_awprot, - input logic[3:0] s_axi_awqos, - input logic[3:0] s_axi_awregion, - input logic[2:0] s_axi_awsize, - output logic s_axi_awready, - input logic s_axi_awvalid, - - output logic[AXI_ADDR_BITS-1:0] m_axi_awaddr, - output logic[1:0] m_axi_awburst, - output logic[3:0] m_axi_awcache, - output logic[AXI_ID_BITS-1:0] m_axi_awid, - output logic[7:0] m_axi_awlen, - output logic[0:0] m_axi_awlock, - output logic[2:0] m_axi_awprot, - output logic[3:0] m_axi_awqos, - output logic[3:0] m_axi_awregion, - output logic[2:0] m_axi_awsize, - input logic m_axi_awready, - output logic m_axi_awvalid, - - // B - output logic[AXI_ID_BITS-1:0] s_axi_bid, - output logic[1:0] s_axi_bresp, - input logic s_axi_bready, - output logic s_axi_bvalid, - - input logic[AXI_ID_BITS-1:0] m_axi_bid, - input logic[1:0] m_axi_bresp, - output logic m_axi_bready, - input logic m_axi_bvalid, - - // W - input logic [AXI_DATA_BITS-1:0] s_axi_wdata, - input logic s_axi_wlast, - input logic [AXI_DATA_BITS/8-1:0] s_axi_wstrb, - output logic s_axi_wready, - input logic s_axi_wvalid, - - output logic [AXI_DATA_BITS-1:0] m_axi_wdata, - output logic m_axi_wlast, - output logic [AXI_DATA_BITS/8-1:0] m_axi_wstrb, - input logic m_axi_wready, - output logic m_axi_wvalid -); - -`ifdef MULT_DDR_CHAN - -localparam integer N_OUTSTANDING_STRIPE = 8 * N_OUTSTANDING; -localparam integer FRAG_LOG_BITS = $clog2(DDR_FRAG_SIZE); -localparam integer BEAT_LOG_BITS = $clog2(AXI_DATA_BITS/8); - -// FSM -typedef enum logic[0:0] {ST_IDLE, ST_PARSE} state_t; -logic[0:0] state_C, state_N; - -logic [AXI_ADDR_BITS-1:0] awaddr_C, awaddr_N; -logic [1:0] awburst_C, awburst_N; -logic [3:0] awcache_C, awcache_N; -logic [1:0] awid_C, awid_N; -logic [7:0] awlen_C, awlen_N; -logic [0:0] awlock_C, awlock_N; -logic [2:0] awprot_C, awprot_N; -logic [3:0] awqos_C, awqos_N; -logic [3:0] awregion_C, awregion_N; -logic [2:0] awsize_C, awsize_N; - -logic [AXI_ADDR_BITS-1:0] paddr_C, paddr_N; -logic [7:0] plen_C, plen_N; -logic done_C, done_N; - -logic [7:0] clen; -logic [7:0] slen; - -logic [AXI_ADDR_BITS-1:0] lsb_mask; -assign lsb_mask = (1 << FRAG_LOG_BITS) - 1; -logic [AXI_ADDR_BITS-1:0] chan_mask; -always_comb begin - chan_mask = 0; - chan_mask[FRAG_LOG_BITS+:N_DDR_CHAN_BITS] = ~0; -end -logic [AXI_ADDR_BITS-1:0] msb_mask; -assign msb_mask = (~lsb_mask) << N_DDR_CHAN_BITS; - -// REG -always_ff @(posedge aclk) begin - if(~aresetn) begin - state_C <= ST_IDLE; - - awaddr_C <= 'X; - awburst_C <= 'X; - awcache_C <= 'X; - awid_C <= 'X; - awlen_C <= 'X; - awlock_C <= 'X; - awprot_C <= 'X; - awqos_C <= 'X; - awregion_C <= 'X; - awsize_C <= 'X; - - paddr_C <= 'X; - plen_C <= 'X; - done_C <= 1'b0; - end - else begin - state_C <= state_N; - - awaddr_C <= awaddr_N; - awburst_C <= awburst_N; - awcache_C <= awcache_N; - awid_C <= awid_N; - awlen_C <= awlen_N; - awlock_C <= awlock_N; - awprot_C <= awprot_N; - awqos_C <= awqos_N; - awregion_C <= awregion_N; - awsize_C <= awsize_N; - - paddr_C <= paddr_N; - plen_C <= plen_N; - done_C <= done_N; - end -end - -// NSL -always_comb begin - state_N = state_C; - - case (state_C) - ST_IDLE: - state_N = s_axi_awvalid ? ST_PARSE : ST_IDLE; - - ST_PARSE: - state_N = (done_C & m_axi_awvalid & m_axi_awready) ? ST_IDLE : ST_PARSE; - - endcase -end - -// DP -always_comb begin - awaddr_N = awaddr_C; - awburst_N = awburst_C; - awcache_N = awcache_C; - awid_N = awid_C; - awlen_N = awlen_C; - awlock_N = awlock_C; - awprot_N = awprot_C; - awqos_N = awqos_C; - awregion_N = awregion_C; - awsize_N = awsize_C; - - paddr_N = paddr_C; - plen_N = plen_C; - done_N = done_C; - - slen = ((DDR_FRAG_SIZE >> BEAT_LOG_BITS) - ((s_axi_awaddr & lsb_mask) >> BEAT_LOG_BITS)) - 1; - clen = ((DDR_FRAG_SIZE >> BEAT_LOG_BITS) - ((awaddr_C & lsb_mask) >> BEAT_LOG_BITS)) - 1; - - // Sink - s_axi_awready = 1'b0; - - // Src - m_axi_awvalid = 1'b0; - - case (state_C) - ST_IDLE: begin - if(s_axi_awvalid) begin - s_axi_awready = 1'b1; - - awaddr_N = s_axi_awaddr; - awburst_N = s_axi_awburst; - awcache_N = s_axi_awcache; - awid_N = s_axi_awid; - awlock_N = s_axi_awlock; - awprot_N = s_axi_awprot; - awqos_N = s_axi_awqos; - awregion_N = s_axi_awregion; - awsize_N = s_axi_awsize; - - paddr_N = (s_axi_awaddr[FRAG_LOG_BITS+:N_DDR_CHAN_BITS] << DDR_CHAN_SIZE) | (s_axi_awaddr & lsb_mask) | ((s_axi_awaddr & msb_mask) >> N_DDR_CHAN_BITS); - awaddr_N = ((s_axi_awaddr >> FRAG_LOG_BITS) << FRAG_LOG_BITS) + DDR_FRAG_SIZE; - if(slen < s_axi_awlen) begin - plen_N = slen; - awlen_N = s_axi_awlen - slen - 1; - done_N = 1'b0; - end - else begin - plen_N = s_axi_awlen; - awlen_N = 0; - done_N = 1'b1; - end - end - end - - ST_PARSE: begin - m_axi_awvalid = 1'b1; - if(m_axi_awready) begin - paddr_N = (awaddr_C[FRAG_LOG_BITS+:N_DDR_CHAN_BITS] << DDR_CHAN_SIZE) | (awaddr_C & lsb_mask) | ((awaddr_C & msb_mask) >> N_DDR_CHAN_BITS); - awaddr_N = ((awaddr_C >> FRAG_LOG_BITS) << FRAG_LOG_BITS) + DDR_FRAG_SIZE; - if(clen < awlen_C) begin - plen_N = clen; - awlen_N = awlen_C - clen - 1; - done_N = 1'b0; - end - else begin - plen_N = awlen_C; - awlen_N = 0; - done_N = 1'b1; - end - end - end - - endcase -end - -// AR -assign m_axi_awaddr = paddr_C; -assign m_axi_awburst = awburst_C; -assign m_axi_awcache = awcache_C; -assign m_axi_awid = awid_C; -assign m_axi_awlen = plen_C; -assign m_axi_awlock = awlock_C; -assign m_axi_awprot = awprot_C; -assign m_axi_awqos = awqos_C; -assign m_axi_awregion = awregion_C; -assign m_axi_awsize = awsize_C; - -metaIntf #(.STYPE(logic)) seq_snk (); -metaIntf #(.STYPE(logic)) seq_src (); - -assign seq_snk.valid = m_axi_awvalid & m_axi_awready; -assign seq_snk.data = done_C; - -// SEQ -queue_meta #(.QDEPTH(N_OUTSTANDING_STRIPE)) inst_seq_que (.aclk(aclk), .aresetn(aresetn), .s_meta(seq_snk), .m_meta(seq_src)); - -// B -assign s_axi_bid = m_axi_bid; -assign s_axi_bresp = m_axi_bresp; -assign s_axi_bvalid = seq_src.data ? m_axi_bvalid : 1'b0; -assign m_axi_bready = seq_src.data ? s_axi_bready : 1'b1; - -assign seq_src.ready = s_axi_bvalid & s_axi_bready; - -// W -assign m_axi_wdata = s_axi_wdata; -assign m_axi_wlast = s_axi_wlast; -assign m_axi_wstrb = s_axi_wstrb; -assign m_axi_wvalid = s_axi_wvalid; -assign s_axi_wready = m_axi_wready; - -/* -ila_wr inst_ila_wr ( - .clk(aclk), - .probe0(awaddr_C[39:0]), // 40 - .probe1(awlen_C), // 8 - .probe2(paddr_C[39:0]), // 40 - .probe3(plen_C), // 8 - .probe4(slen), // 8 - .probe5(clen), // 8 - .probe6(state_C), - .probe7(s_axi_awaddr[39:0]), // 40 - .probe8(s_axi_awlen), // 8 - .probe9(s_axi_awvalid), - .probe10(s_axi_awready), - .probe11(m_axi_awaddr[39:0]), // 40 - .probe12(m_axi_awlen), // 8 - .probe13(m_axi_awvalid), - .probe14(m_axi_awready), - .probe15(s_axi_wvalid), - .probe16(s_axi_wready), - .probe17(s_axi_wstrb), // 64 - .probe18(s_axi_wdata), // 512 - .probe19(s_axi_bvalid), - .probe20(s_axi_bready) -); -*/ - -`else - -assign m_axi_awaddr = s_axi_awaddr; -assign m_axi_awburst = s_axi_awburst; -assign m_axi_awcache = s_axi_awcache; -assign m_axi_awid = s_axi_awid; -assign m_axi_awlen = s_axi_awlen; -assign m_axi_awlock = s_axi_awlock; -assign m_axi_awprot = s_axi_awprot; -assign m_axi_awqos = s_axi_awqos; -assign m_axi_awregion = s_axi_awregion; -assign m_axi_awsize = s_axi_awsize; -assign m_axi_awvalid = s_axi_awvalid; -assign s_axi_awready = m_axi_awready; -assign m_axi_wdata = s_axi_wdata; -assign m_axi_wlast = s_axi_wlast; -assign m_axi_wstrb = s_axi_wstrb; -assign s_axi_wready = m_axi_wready; -assign m_axi_wvalid = s_axi_wvalid; -assign s_axi_bid = m_axi_bid; -assign s_axi_bresp = m_axi_bresp; -assign m_axi_bready = s_axi_bready; -assign s_axi_bvalid = m_axi_bvalid; - -`endif - -endmodule \ No newline at end of file diff --git a/hw/hdl/cdma_common/axi_stripe.sv b/hw/hdl/stripe/axi_stripe.sv similarity index 86% rename from hw/hdl/cdma_common/axi_stripe.sv rename to hw/hdl/stripe/axi_stripe.sv index f12a5e4..b0b41f8 100644 --- a/hw/hdl/cdma_common/axi_stripe.sv +++ b/hw/hdl/stripe/axi_stripe.sv @@ -45,8 +45,11 @@ AXI4 m_axi_int(); axi_reg_array #(.N_STAGES(N_STAGES)) inst_s_reg_arr (.aclk(aclk), .aresetn(aresetn), .s_axi(s_axi), .m_axi(s_axi_int)); axi_reg_array #(.N_STAGES(N_STAGES)) inst_m_reg_arr (.aclk(aclk), .aresetn(aresetn), .s_axi(m_axi_int), .m_axi(m_axi)); -// RD -axi_stripe_rd inst_axi_stripe_rd ( +metaIntf #(.STYPE(logic[1+N_DDR_CHAN_BITS+8-1:0])) mux_r (); +metaIntf #(.STYPE(logic[1+N_DDR_CHAN_BITS+8-1:0])) mux_b (); + +// AR +axi_stripe_a inst_axi_stripe_ar ( .aclk(aclk), .aresetn(aresetn), @@ -77,6 +80,14 @@ axi_stripe_rd inst_axi_stripe_rd ( .m_axi_arready(m_axi_int.arready), .m_axi_arvalid(m_axi_int.arvalid), + // Mux + .mux(mux_r) +); + +axi_stripe_r inst_axi_stripe_r ( + .aclk(aclk), + .aresetn(aresetn), + // R .s_axi_rdata(s_axi_int.rdata), .s_axi_rid(s_axi_int.rid), @@ -90,11 +101,14 @@ axi_stripe_rd inst_axi_stripe_rd ( .m_axi_rlast(m_axi_int.rlast), .m_axi_rresp(m_axi_int.rresp), .m_axi_rready(m_axi_int.rready), - .m_axi_rvalid(m_axi_int.rvalid) -); + .m_axi_rvalid(m_axi_int.rvalid), -// WR -axi_stripe_wr inst_axi_stripe_wr ( + // Mux + .mux(mux_r) +); + +// AW +axi_stripe_a inst_axi_stripe_aw ( .aclk(aclk), .aresetn(aresetn), @@ -125,6 +139,15 @@ axi_stripe_wr inst_axi_stripe_wr ( .m_axi_awready(m_axi_int.awready), .m_axi_awvalid(m_axi_int.awvalid), + // Mux + .mux(mux_b) +); + +// B +axi_stripe_b inst_axi_stripe_b ( + .aclk(aclk), + .aresetn(aresetn), + // B .s_axi_bid(s_axi_int.bid), .s_axi_bresp(s_axi_int.bresp), @@ -136,18 +159,15 @@ axi_stripe_wr inst_axi_stripe_wr ( .m_axi_bready(m_axi_int.bready), .m_axi_bvalid(m_axi_int.bvalid), - // W - .s_axi_wdata(s_axi_int.wdata), - .s_axi_wlast(s_axi_int.wlast), - .s_axi_wstrb(s_axi_int.wstrb), - .s_axi_wready(s_axi_int.wready), - .s_axi_wvalid(s_axi_int.wvalid), + // Mux + .mux(mux_b) +); - .m_axi_wdata(m_axi_int.wdata), - .m_axi_wlast(m_axi_int.wlast), - .m_axi_wstrb(m_axi_int.wstrb), - .m_axi_wready(m_axi_int.wready), - .m_axi_wvalid(m_axi_int.wvalid) -); +// W +assign m_axi_int.wdata = s_axi_int.wdata; +assign m_axi_int.wstrb = s_axi_int.wstrb; +assign m_axi_int.wstrb = s_axi_int.wstrb; +assign m_axi_int.wvalid = s_axi_int.wvalid; +assign s_axi_int.wready = m_axi_int.wready; endmodule \ No newline at end of file diff --git a/hw/hdl/stripe/axi_stripe_a.sv b/hw/hdl/stripe/axi_stripe_a.sv new file mode 100644 index 0000000..cd9c6b7 --- /dev/null +++ b/hw/hdl/stripe/axi_stripe_a.sv @@ -0,0 +1,302 @@ +/** + * Copyright (c) 2021, Systems Group, ETH Zurich + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +`timescale 1ns / 1ps + +import lynxTypes::*; + +module axi_stripe_a ( + input logic aclk, + input logic aresetn, + + // AR + input logic[AXI_ADDR_BITS-1:0] s_axi_aaddr, + input logic[1:0] s_axi_aburst, + input logic[3:0] s_axi_acache, + input logic[AXI_ID_BITS-1:0] s_axi_aid, + input logic[7:0] s_axi_alen, + input logic[0:0] s_axi_alock, + input logic[2:0] s_axi_aprot, + input logic[3:0] s_axi_aqos, + input logic[3:0] s_axi_aregion, + input logic[2:0] s_axi_asize, + output logic s_axi_aready, + input logic s_axi_avalid, + + output logic[AXI_ADDR_BITS-1:0] m_axi_aaddr, + output logic[1:0] m_axi_aburst, + output logic[3:0] m_axi_acache, + output logic[AXI_ID_BITS-1:0] m_axi_aid, + output logic[7:0] m_axi_alen, + output logic[0:0] m_axi_alock, + output logic[2:0] m_axi_aprot, + output logic[3:0] m_axi_aqos, + output logic[3:0] m_axi_aregion, + output logic[2:0] m_axi_asize, + input logic m_axi_aready, + output logic m_axi_avalid, + + // Mux + metaIntf.m mux +); + +`ifdef MULT_DDR_CHAN + +localparam integer N_OUTSTANDING_STRIPE = 8 * N_OUTSTANDING; +localparam integer FRAG_LOG_BITS = $clog2(DDR_FRAG_SIZE); +localparam integer BEAT_LOG_BITS = $clog2(AXI_DATA_BITS/8); +localparam integer BLEN_BITS = LEN_BITS - BEAT_LOG_BITS; + +// FSM +typedef enum logic[0:0] {ST_IDLE, ST_PARSE} state_t; +logic[0:0] state_C, state_N; + +logic [AXI_ADDR_BITS-1:0] aaddr_C, aaddr_N; +logic [1:0] aburst_C, aburst_N; +logic [3:0] acache_C, acache_N; +logic [N_DDR_CHAN_BITS-1:0] aid_C, aid_N; +logic [7:0] alen_C, alen_N; +logic [0:0] alock_C, alock_N; +logic [2:0] aprot_C, aprot_N; +logic [3:0] aqos_C, aqos_N; +logic [3:0] aregion_C, aregion_N; +logic [2:0] asize_C, asize_N; + +logic [AXI_ADDR_BITS-1:0] paddr_C, paddr_N; +logic [7:0] plen_C, plen_N; +logic done_C, done_N; + +logic [7:0] clen; +logic [7:0] slen; + +logic [AXI_ADDR_BITS-1:0] lsb_mask; +assign lsb_mask = (1 << FRAG_LOG_BITS) - 1; +logic [AXI_ADDR_BITS-1:0] chan_mask; +always_comb begin + chan_mask = 0; + chan_mask[FRAG_LOG_BITS+:N_DDR_CHAN_BITS] = ~0; +end +logic [AXI_ADDR_BITS-1:0] msb_mask; +assign msb_mask = (~lsb_mask) << N_DDR_CHAN_BITS; + +metaIntf #(.STYPE(logic[1+N_DDR_CHAN_BITS+8-1:0])) seq_snk (); // ctl, id, len + +// REG +always_ff @(posedge aclk) begin + if(~aresetn) begin + state_C <= ST_IDLE; + + aaddr_C <= 'X; + aburst_C <= 'X; + acache_C <= 'X; + aid_C <= 'X; + alen_C <= 'X; + alock_C <= 'X; + aprot_C <= 'X; + aqos_C <= 'X; + aregion_C <= 'X; + asize_C <= 'X; + + paddr_C <= 'X; + plen_C <= 'X; + done_C <= 1'b0; + end + else begin + state_C <= state_N; + + aaddr_C <= aaddr_N; + aburst_C <= aburst_N; + acache_C <= acache_N; + aid_C <= aid_N; + alen_C <= alen_N; + alock_C <= alock_N; + aprot_C <= aprot_N; + aqos_C <= aqos_N; + aregion_C <= aregion_N; + asize_C <= asize_N; + + paddr_C <= paddr_N; + plen_C <= plen_N; + done_C <= done_N; + end +end + +// NSL +always_comb begin + state_N = state_C; + + case (state_C) + ST_IDLE: + state_N = s_axi_avalid ? ST_PARSE : ST_IDLE; + + ST_PARSE: + state_N = (done_C & m_axi_aready & seq_snk.ready) ? ST_IDLE : ST_PARSE; + + endcase +end + +// DP +always_comb begin + aaddr_N = aaddr_C; + aburst_N = aburst_C; + acache_N = acache_C; + aid_N = aid_C; + alen_N = alen_C; + alock_N = alock_C; + aprot_N = aprot_C; + aqos_N = aqos_C; + aregion_N = aregion_C; + asize_N = asize_C; + + paddr_N = paddr_C; + plen_N = plen_C; + done_N = done_C; + + slen = ((DDR_FRAG_SIZE >> BEAT_LOG_BITS) - ((s_axi_aaddr & lsb_mask) >> BEAT_LOG_BITS)) - 1; + clen = ((DDR_FRAG_SIZE >> BEAT_LOG_BITS) - ((aaddr_C & lsb_mask) >> BEAT_LOG_BITS)) - 1; + + // Sink + s_axi_aready = 1'b0; + + // Src + m_axi_avalid = 1'b0; + + // Seq + seq_snk.valid = 1'b0; + seq_snk.data = {done_C, aid_C, plen_C}; + + case (state_C) + ST_IDLE: begin + if(s_axi_avalid) begin + s_axi_aready = 1'b1; + + aaddr_N = s_axi_aaddr; + aburst_N = s_axi_aburst; + acache_N = s_axi_acache; + aid_N = s_axi_aid; + alock_N = s_axi_alock; + aprot_N = s_axi_aprot; + aqos_N = s_axi_aqos; + aregion_N = s_axi_aregion; + asize_N = s_axi_asize; + + paddr_N = (s_axi_aaddr[FRAG_LOG_BITS+:N_DDR_CHAN_BITS] << DDR_CHAN_SIZE) | (s_axi_aaddr & lsb_mask) | ((s_axi_aaddr & msb_mask) >> N_DDR_CHAN_BITS); + aaddr_N = ((s_axi_aaddr >> FRAG_LOG_BITS) << FRAG_LOG_BITS) + DDR_FRAG_SIZE; + if(slen < s_axi_alen) begin + plen_N = slen; + alen_N = s_axi_alen - slen - 1; + aid_N = s_axi_aaddr[FRAG_LOG_BITS+:N_DDR_CHAN_BITS]; + done_N = 1'b0; + end + else begin + plen_N = s_axi_alen; + alen_N = 0; + aid_N = s_axi_aaddr[FRAG_LOG_BITS+:N_DDR_CHAN_BITS]; + done_N = 1'b1; + end + end + end + + ST_PARSE: begin + if(m_axi_aready && seq_snk.ready) begin + m_axi_avalid = 1'b1; + seq_snk.valid = 1'b1; + + paddr_N = (aaddr_C[FRAG_LOG_BITS+:N_DDR_CHAN_BITS] << DDR_CHAN_SIZE) | (aaddr_C & lsb_mask) | ((aaddr_C & msb_mask) >> N_DDR_CHAN_BITS); + aaddr_N = ((aaddr_C >> FRAG_LOG_BITS) << FRAG_LOG_BITS) + DDR_FRAG_SIZE; + if(clen < alen_C) begin + plen_N = clen; + alen_N = alen_C - clen - 1; + aid_N = aaddr_C[FRAG_LOG_BITS+:N_DDR_CHAN_BITS]; + done_N = 1'b0; + end + else begin + plen_N = alen_C; + alen_N = 0; + aid_N = aaddr_C[FRAG_LOG_BITS+:N_DDR_CHAN_BITS]; + done_N = 1'b1; + end + end + end + + endcase +end + +// AR +assign m_axi_aaddr = paddr_C; +assign m_axi_aburst = aburst_C; +assign m_axi_acache = acache_C; +assign m_axi_aid = aid_C; +assign m_axi_alen = plen_C; +assign m_axi_alock = alock_C; +assign m_axi_aprot = aprot_C; +assign m_axi_aqos = aqos_C; +assign m_axi_aregion = aregion_C; +assign m_axi_asize = asize_C; + +// SEQ +queue_meta #(.QDEPTH(N_OUTSTANDING_STRIPE)) inst_seq_que (.aclk(aclk), .aresetn(aresetn), .s_meta(seq_snk), .m_meta(mux)); + +/* +ila_rd inst_ila_rd ( + .clk(aclk), + .probe0(aaddr_C[39:0]), // 40 + .probe1(alen_C), // 8 + .probe2(paddr_C[39:0]), // 40 + .probe3(plen_C), // 8 + .probe4(slen), // 8 + .probe5(clen), // 8 + .probe6(state_C), + .probe7(s_axi_aaddr[39:0]), // 40 + .probe8(s_axi_alen), // 8 + .probe9(s_axi_avalid), + .probe10(s_axi_aready), + .probe11(m_axi_aaddr[39:0]), // 40 + .probe12(m_axi_alen), // 8 + .probe13(m_axi_avalid), + .probe14(m_axi_aready) +); +*/ + +`else + +assign m_axi_aaddr = s_axi_aaddr; +assign m_axi_aburst = s_axi_aburst; +assign m_axi_acache = s_axi_acache; +assign m_axi_aid = s_axi_aid; +assign m_axi_alen = s_axi_alen; +assign m_axi_alock = s_axi_alock; +assign m_axi_aprot = s_axi_aprot; +assign m_axi_aqos = s_axi_aqos; +assign m_axi_aregion = s_axi_aregion; +assign m_axi_asize = s_axi_asize; +assign m_axi_avalid = s_axi_avalid; +assign s_axi_aready = m_axi_aready; + +`endif + +endmodule \ No newline at end of file diff --git a/hw/hdl/stripe/axi_stripe_b.sv b/hw/hdl/stripe/axi_stripe_b.sv new file mode 100644 index 0000000..895d794 --- /dev/null +++ b/hw/hdl/stripe/axi_stripe_b.sv @@ -0,0 +1,148 @@ +/** + * Copyright (c) 2021, Systems Group, ETH Zurich + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +`timescale 1ns / 1ps + +import lynxTypes::*; + +module axi_stripe_r ( + input logic aclk, + input logic aresetn, + + // B + input logic [AXI_ID_BITS-1:0] s_axi_bid, + input logic [1:0] s_axi_bresp, + input logic s_axi_bvalid, + output logic s_axi_bready, + + output logic [AXI_ID_BITS-1:0] m_axi_bid, + output logic [1:0] m_axi_bresp, + output logic m_axi_bvalid, + input logic m_axi_bready, + + // Mux + metaIntf.s mux +); + +// -- Constants +localparam integer BEAT_LOG_BITS = $clog2(DATA_BITS/8); +localparam integer BLEN_BITS = LEN_BITS - BEAT_LOG_BITS; + +// -- FSM +typedef enum logic[0:0] {ST_IDLE, ST_MUX} state_t; +logic [0:0] state_C, state_N; + +// -- Internal regs +logic ctl_C, ctl_N; +logic [N_DDR_CHAN_BITS-1:0] id_C, id_N; + +// REG +always_ff @(posedge aclk) begin + if(~aresetn) begin + state_C <= ST_IDLE; + id_C <= 'X; + ctl_C <= 'X; + end + else begin + state_C <= state_N; + id_C <= id_N; + ctl_C <= ctl_N; + end +end + +// NSL +always_comb begin + state_N = state_C; + + case (state_C) + ST_IDLE: + state_N = mux.valid ? ST_MUX : ST_IDLE; + + ST_MUX: + state_N = (m_axi_bvalid && m_axi_bready) ? (mux.valid ? ST_MUX : ST_IDLE) : ST_MUX; + + endcase +end + +// DP +always_comb begin + id_N = id_C; + ctl_N = ctl_C; + + mux.ready = 1'b0; + + bready_src = 0; + + m_axi_bvalid = 1'b0; + m_axi_bresp = bresp_src[id_C]; + + case (state_C) + ST_IDLE: begin + if(mux.valid) begin + mux.ready = 1'b1; + id_N = mux.data[8]; + ctl_N = mux.data[9]; + end + end + + ST_MUX: begin + m_axi_bvalid = bvalid_src[id_C]; + bready_src[id_C] = m_axi_bready; + + if(m_axi_bvalid && m_axi_bready) begin + if(mux.valid) begin + mux.ready = 1'b1; + id_N = mux.data[8]; + ctl_N = mux.data[9]; + end + end + end + + endcase + +end + +// Reorder buffers +for(genvar i = 0; i < N_DDR_CHAN; i++) begin + assign bvalid_sink[i] = (i == s_axi_bid) ? s_axi_bvalid : 1'b0; + assign bresp_sink[i] = s_axi_rresp; + + assign s_axi_bready = bready_sink[s_axi_bid]; + + axis_data_fifo_512_stripe_b inst_reorder ( + .s_axis_aresetn(aresetn), + .s_axis_aclk(aclk), + .s_axis_tvalid(bvalid_sink[i]), + .s_axis_tready(bready_sink[i]), + .s_axis_tuser(bresp_sink[i]), + .m_axis_tvalid(bvalid_src[i]), + .m_axis_tready(bready_src[i]), + .m_axis_tuser(bresp_src[i]) + ); +end + +endmodule \ No newline at end of file diff --git a/hw/hdl/stripe/axi_stripe_r.sv b/hw/hdl/stripe/axi_stripe_r.sv new file mode 100644 index 0000000..088925d --- /dev/null +++ b/hw/hdl/stripe/axi_stripe_r.sv @@ -0,0 +1,171 @@ +/** + * Copyright (c) 2021, Systems Group, ETH Zurich + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +`timescale 1ns / 1ps + +import lynxTypes::*; + +module axi_stripe_r ( + input logic aclk, + input logic aresetn, + + // R + input logic [AXI_DATA_BITS-1:0] s_axi_rdata, + input logic [AXI_ID_BITS-1:0] s_axi_rid, + input logic s_axi_rlast, + input logic [1:0] s_axi_rresp, + input logic s_axi_rvalid, + output logic s_axi_rready, + + output logic [AXI_DATA_BITS-1:0] m_axi_rdata, + output logic [AXI_ID_BITS-1:0] m_axi_rid, + output logic m_axi_rlast, + output logic [1:0] m_axi_rresp, + output logic m_axi_rvalid, + input logic m_axi_rready, + + // Mux + metaIntf.s mux +); + +// -- Constants +localparam integer BEAT_LOG_BITS = $clog2(DATA_BITS/8); +localparam integer BLEN_BITS = LEN_BITS - BEAT_LOG_BITS; + +// -- FSM +typedef enum logic[0:0] {ST_IDLE, ST_MUX} state_t; +logic [0:0] state_C, state_N; + +// -- Internal regs +logic [7:0] cnt_C, cnt_N; +logic ctl_C, ctl_N; +logic [N_DDR_CHAN_BITS-1:0] id_C, id_N; + +// REG +always_ff @(posedge aclk) begin + if(~aresetn) begin + state_C <= ST_IDLE; + cnt_C <= 0; + id_C <= 'X; + ctl_C <= 'X; + end + else begin + state_C <= state_N; + cnt_C <= cnt_N; + id_C <= id_N; + ctl_C <= ctl_N; + end +end + +// NSL +always_comb begin + state_N = state_C; + + case (state_C) + ST_IDLE: + state_N = mux.valid ? ST_MUX : ST_IDLE; + + ST_MUX: + state_N = ((cnt_C == 0) && m_axi_rvalid && m_axi_rready) ? (mux.valid ? ST_MUX : ST_IDLE) : ST_MUX; + + endcase +end + +// DP +always_comb begin + cnt_N = cnt_C; + id_N = id_C; + ctl_N = ctl_C; + + mux.ready = 1'b0; + + rready_src = 0; + + m_axi_rvalid = 1'b0; + m_axi_rdata = rdata_src[id_C]; + m_axi_rresp = rresp_src[id_C]; + m_axi_rlast = (cnt_C == 0) & ctl_C; + + case (state_C) + ST_IDLE: begin + if(mux.valid) begin + mux.ready = 1'b1; + cnt_N = mux.data[7:0]; + id_N = mux.data[8]; + ctl_N = mux.data[9]; + end + end + + ST_MUX: begin + m_axi_rvalid = rvalid_src[id_C]; + rready_src[id_C] = m_axi_rready; + + if(m_axi_rvalid && m_axi_rready) begin + if(cnt_C == 0) begin + if(mux.valid) begin + mux.ready = 1'b1; + cnt_N = mux.data[7:0]; + id_N = mux.data[8]; + ctl_N = mux.data[9]; + end + end + else begin + cnt_N = cnt_C - 1; + end + end + end + + endcase + +end + +// Reorder buffers +for(genvar i = 0; i < N_DDR_CHAN; i++) begin + assign rvalid_sink[i] = (i == s_axi_rid) ? s_axi_rvalid : 1'b0; + assign rdata_sink[i] = s_axi_rdata; + assign rlast_sink[i] = s_axi_rlast; + assign rresp_sink[i] = s_axi_rresp; + + assign s_axi_rready = rready_sink[s_axi_rid]; + + axis_data_fifo_512_stripe_r inst_reorder ( + .s_axis_aresetn(aresetn), + .s_axis_aclk(aclk), + .s_axis_tvalid(rvalid_sink[i]), + .s_axis_tready(rready_sink[i]), + .s_axis_tdata(rdata_sink[i]), + .s_axis_tlast(rlast_sink[i]), + .s_axis_tuser(rresp_sink[i]), + .m_axis_tvalid(rvalid_src[i]), + .m_axis_tready(rready_src[i]), + .m_axis_tdata(rdata_src[i]), + .m_axis_tlast(rlast_src[i]), + .m_axis_tuser(rresp_src[i]) + ); +end + +endmodule \ No newline at end of file diff --git a/hw/scripts/wr_hdl/template_gen/cyt_top_u200.txt b/hw/scripts/wr_hdl/template_gen/cyt_top_u200.txt index 1569388..520befa 100644 --- a/hw/scripts/wr_hdl/template_gen/cyt_top_u200.txt +++ b/hw/scripts/wr_hdl/template_gen/cyt_top_u200.txt @@ -278,9 +278,9 @@ module cyt_top ( // PR streams AXI4S axis_pr(); - wire [1:0][31:0] axis_pr_data; - wire [1:0] axis_pr_ready; - wire [1:0] axis_pr_valid; + wire [N_REG_PR:0][31:0] axis_pr_data; + wire [N_REG_PR:0] axis_pr_ready; + wire [N_REG_PR:0] axis_pr_valid; // PR ICAP wire [31:0] icap_out; diff --git a/hw/scripts/wr_hdl/template_gen/cyt_top_u250.txt b/hw/scripts/wr_hdl/template_gen/cyt_top_u250.txt index d6070e1..3e6921c 100644 --- a/hw/scripts/wr_hdl/template_gen/cyt_top_u250.txt +++ b/hw/scripts/wr_hdl/template_gen/cyt_top_u250.txt @@ -278,9 +278,9 @@ module cyt_top ( // PR streams AXI4S axis_pr(); - wire [1:0][31:0] axis_pr_data; - wire [1:0] axis_pr_ready; - wire [1:0] axis_pr_valid; + wire [N_REG_PR:0][31:0] axis_pr_data; + wire [N_REG_PR:0] axis_pr_ready; + wire [N_REG_PR:0] axis_pr_valid; // PR ICAP wire [31:0] icap_out; diff --git a/hw/scripts/wr_hdl/template_gen/cyt_top_u280.txt b/hw/scripts/wr_hdl/template_gen/cyt_top_u280.txt index 9dec9aa..34cec99 100644 --- a/hw/scripts/wr_hdl/template_gen/cyt_top_u280.txt +++ b/hw/scripts/wr_hdl/template_gen/cyt_top_u280.txt @@ -246,9 +246,9 @@ module cyt_top ( // PR streams AXI4S axis_pr(); - wire [1:0][31:0] axis_pr_data; - wire [1:0] axis_pr_ready; - wire [1:0] axis_pr_valid; + wire [N_REG_PR:0][31:0] axis_pr_data; + wire [N_REG_PR:0] axis_pr_ready; + wire [N_REG_PR:0] axis_pr_valid; // PR ICAP wire [31:0] icap_out; diff --git a/hw/scripts/wr_hdl/template_gen/cyt_top_u50.txt b/hw/scripts/wr_hdl/template_gen/cyt_top_u50.txt index ce7ba61..eeace91 100644 --- a/hw/scripts/wr_hdl/template_gen/cyt_top_u50.txt +++ b/hw/scripts/wr_hdl/template_gen/cyt_top_u50.txt @@ -206,9 +206,9 @@ module cyt_top ( // PR streams AXI4S axis_pr(); - wire [1:0][31:0] axis_pr_data; - wire [1:0] axis_pr_ready; - wire [1:0] axis_pr_valid; + wire [N_REG_PR:0][31:0] axis_pr_data; + wire [N_REG_PR:0] axis_pr_ready; + wire [N_REG_PR:0] axis_pr_valid; // PR ICAP wire [31:0] icap_out; diff --git a/hw/scripts/wr_hdl/template_gen/cyt_top_u55c.txt b/hw/scripts/wr_hdl/template_gen/cyt_top_u55c.txt index 3c8aa4b..fa01985 100644 --- a/hw/scripts/wr_hdl/template_gen/cyt_top_u55c.txt +++ b/hw/scripts/wr_hdl/template_gen/cyt_top_u55c.txt @@ -206,9 +206,9 @@ module cyt_top ( // PR streams AXI4S axis_pr(); - wire [1:0][31:0] axis_pr_data; - wire [1:0] axis_pr_ready; - wire [1:0] axis_pr_valid; + wire [N_REG_PR:0][31:0] axis_pr_data; + wire [N_REG_PR:0] axis_pr_ready; + wire [N_REG_PR:0] axis_pr_valid; // PR ICAP wire [31:0] icap_out; diff --git a/hw/scripts/wr_hdl/template_gen/cyt_top_vcu118.txt b/hw/scripts/wr_hdl/template_gen/cyt_top_vcu118.txt index a9bf5f6..f24c8a2 100644 --- a/hw/scripts/wr_hdl/template_gen/cyt_top_vcu118.txt +++ b/hw/scripts/wr_hdl/template_gen/cyt_top_vcu118.txt @@ -235,9 +235,9 @@ module cyt_top ( // PR streams AXI4S axis_pr(); - wire [1:0][31:0] axis_pr_data; - wire [1:0] axis_pr_ready; - wire [1:0] axis_pr_valid; + wire [N_REG_PR:0][31:0] axis_pr_data; + wire [N_REG_PR:0] axis_pr_ready; + wire [N_REG_PR:0] axis_pr_valid; // PR ICAP wire [31:0] icap_out; diff --git a/hw/scripts/wr_hdl/template_gen/lynx_pkg.txt b/hw/scripts/wr_hdl/template_gen/lynx_pkg.txt index 8aefe32..654ec78 100644 --- a/hw/scripts/wr_hdl/template_gen/lynx_pkg.txt +++ b/hw/scripts/wr_hdl/template_gen/lynx_pkg.txt @@ -113,7 +113,7 @@ package lynxTypes; parameter integer AXI_NET_BITS = 512; parameter integer AXI_DDR_BITS = 512; parameter integer AXI_TLB_BITS = 128; - parameter integer AXI_ID_BITS = 1; + parameter integer AXI_ID_BITS = 6; // TLB ram parameter integer TLB_S_ORDER = {{ cnfg.tlbs_s }}; @@ -156,6 +156,7 @@ package lynxTypes; parameter integer N_REG_ECI_S0 = 3; parameter integer N_REG_ECI_S1 = 2; parameter integer N_REG_DYN_DCPL = 4; + parameter integer N_REG_PR = 2; // Network parameter integer ARP_LUP_REQ_BITS = 32; diff --git a/hw/scripts/wr_hdl/template_gen/top_shell.txt b/hw/scripts/wr_hdl/template_gen/top_shell.txt index 049a778..94f677f 100644 --- a/hw/scripts/wr_hdl/template_gen/top_shell.txt +++ b/hw/scripts/wr_hdl/template_gen/top_shell.txt @@ -248,24 +248,26 @@ .m_axis_tlast() ); - pr_reg_slice inst_pr_slice ( - .aclk(pclk), - .aresetn(presetn), - .s_axis_tvalid(axis_pr_valid[0]), - .s_axis_tready(axis_pr_ready[0]), - .s_axis_tdata(axis_pr_data[0]), - .m_axis_tvalid(axis_pr_valid[1]), - .m_axis_tready(axis_pr_ready[1]), - .m_axis_tdata(axis_pr_data[1]) - ); + for(genvar i = 0; i < N_REG_PR; i++) begin + pr_reg_slice inst_pr_slice ( + .aclk(pclk), + .aresetn(presetn), + .s_axis_tvalid(axis_pr_valid[i]), + .s_axis_tready(axis_pr_ready[i]), + .s_axis_tdata(axis_pr_data[i]), + .m_axis_tvalid(axis_pr_valid[i+1]), + .m_axis_tready(axis_pr_ready[i+1]), + .m_axis_tdata(axis_pr_data[i+1]) + ); + end // Partial reconfiguration - assign icap_csn = ~axis_pr_valid[1]; - assign axis_pr_ready[1] = 1'b1; - assign icap_data = {axis_pr_data[1][24], axis_pr_data[1][25], axis_pr_data[1][26], axis_pr_data[1][27], axis_pr_data[1][28], axis_pr_data[1][29], axis_pr_data[1][30], axis_pr_data[1][31], - axis_pr_data[1][16], axis_pr_data[1][17], axis_pr_data[1][18], axis_pr_data[1][19], axis_pr_data[1][20], axis_pr_data[1][21], axis_pr_data[1][22], axis_pr_data[1][23], - axis_pr_data[1][8], axis_pr_data[1][9], axis_pr_data[1][10], axis_pr_data[1][11], axis_pr_data[1][12], axis_pr_data[1][13], axis_pr_data[1][14], axis_pr_data[1][15], - axis_pr_data[1][0], axis_pr_data[1][1], axis_pr_data[1][2], axis_pr_data[1][3], axis_pr_data[1][4], axis_pr_data[1][5], axis_pr_data[1][6], axis_pr_data[1][7]}; + assign icap_csn = ~axis_pr_valid[N_REG_PR]; + assign axis_pr_ready[N_REG_PR] = 1'b1; + assign icap_data = {axis_pr_data[N_REG_PR][24], axis_pr_data[N_REG_PR][25], axis_pr_data[N_REG_PR][26], axis_pr_data[N_REG_PR][27], axis_pr_data[N_REG_PR][28], axis_pr_data[N_REG_PR][29], axis_pr_data[N_REG_PR][30], axis_pr_data[N_REG_PR][31], + axis_pr_data[N_REG_PR][16], axis_pr_data[N_REG_PR][17], axis_pr_data[N_REG_PR][18], axis_pr_data[N_REG_PR][19], axis_pr_data[N_REG_PR][20], axis_pr_data[N_REG_PR][21], axis_pr_data[N_REG_PR][22], axis_pr_data[N_REG_PR][23], + axis_pr_data[N_REG_PR][8], axis_pr_data[N_REG_PR][9], axis_pr_data[N_REG_PR][10], axis_pr_data[N_REG_PR][11], axis_pr_data[N_REG_PR][12], axis_pr_data[N_REG_PR][13], axis_pr_data[N_REG_PR][14], axis_pr_data[N_REG_PR][15], + axis_pr_data[N_REG_PR][0], axis_pr_data[N_REG_PR][1], axis_pr_data[N_REG_PR][2], axis_pr_data[N_REG_PR][3], axis_pr_data[N_REG_PR][4], axis_pr_data[N_REG_PR][5], axis_pr_data[N_REG_PR][6], axis_pr_data[N_REG_PR][7]}; ICAPE3 #( .ICAP_AUTO_SWITCH("DISABLE"),