rdma cmplt compiling, pid hash.

This commit is contained in:
kodario 2023-06-12 18:02:24 +02:00
parent 24eae14790
commit 789214db94
15 changed files with 142 additions and 137 deletions

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@ -330,6 +330,7 @@ extern long int eost;
#define PR_BATCH_SIZE (2 * 1024 * 1024) #define PR_BATCH_SIZE (2 * 1024 * 1024)
#define USER_HASH_TABLE_ORDER 8 #define USER_HASH_TABLE_ORDER 8
#define PID_HASH_TABLE_ORDER 8
/* PID */ /* PID */
#define N_CPID_MAX 64 #define N_CPID_MAX 64
@ -531,7 +532,7 @@ struct xdma_engine {
/* Inode */ /* Inode */
struct cid_entry { struct cid_entry {
struct hlist_node entry; struct hlist_node entry;
uint64_t ino; pid_t pid;
int32_t cpid; int32_t cpid;
}; };
@ -556,7 +557,8 @@ struct pr_pages {
struct page **pages; struct page **pages;
}; };
extern struct hlist_head cid_map[MAX_N_REGIONS][1 << (USER_HASH_TABLE_ORDER)]; // cid mapping /* PID tables */
extern struct hlist_head pid_cpid_map[MAX_N_REGIONS][1 << (PID_HASH_TABLE_ORDER)];
/* User tables */ /* User tables */
extern struct hlist_head user_lbuff_map[MAX_N_REGIONS][1 << (USER_HASH_TABLE_ORDER)]; // large alloc extern struct hlist_head user_lbuff_map[MAX_N_REGIONS][1 << (USER_HASH_TABLE_ORDER)]; // large alloc

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@ -443,7 +443,7 @@ int init_fpga_devices(struct bus_drvdata *d)
d->fpga_dev[i].cdev.ops = &fpga_fops; d->fpga_dev[i].cdev.ops = &fpga_fops;
// Init hash // Init hash
hash_init(cid_map[i]); hash_init(pid_cpid_map[i]);
hash_init(user_lbuff_map[i]); hash_init(user_lbuff_map[i]);
hash_init(user_sbuff_map[i]); hash_init(user_sbuff_map[i]);

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@ -36,7 +36,7 @@
|_| |_|
*/ */
struct hlist_head cid_map[MAX_N_REGIONS][1 << (USER_HASH_TABLE_ORDER)]; // cid mapping struct hlist_head pid_cpid_map[MAX_N_REGIONS][1 << (USER_HASH_TABLE_ORDER)]; // cid mapping
/** /**
* @brief Acquire a region * @brief Acquire a region
@ -63,19 +63,19 @@ int fpga_open(struct inode *inode, struct file *file)
*/ */
int fpga_release(struct inode *inode, struct file *file) int fpga_release(struct inode *inode, struct file *file)
{ {
uint64_t ino;
int32_t cpid; int32_t cpid;
struct cid_entry *tmp_cid; struct cid_entry *tmp_cid;
pid_t pid;
int minor = iminor(inode); int minor = iminor(inode);
struct fpga_dev *d = container_of(inode->i_cdev, struct fpga_dev, cdev); struct fpga_dev *d = container_of(inode->i_cdev, struct fpga_dev, cdev);
BUG_ON(!d); BUG_ON(!d);
ino = inode->i_ino; pid = current->pid;
hash_for_each_possible(cid_map[d->id], tmp_cid, entry, ino) { hash_for_each_possible(pid_cpid_map[d->id], tmp_cid, entry, pid) {
if(tmp_cid->ino == ino) { if(tmp_cid->pid == pid) {
cpid = tmp_cid->cpid; cpid = tmp_cid->cpid;
// unamp all leftover user pages // unamp all leftover user pages
@ -129,6 +129,7 @@ long fpga_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
int ret_val, i; int ret_val, i;
uint64_t tmp[MAX_USER_WORDS]; uint64_t tmp[MAX_USER_WORDS];
uint64_t cpid; uint64_t cpid;
pid_t pid;
struct cid_entry *tmp_cid; struct cid_entry *tmp_cid;
struct fpga_dev *d = (struct fpga_dev *)file->private_data; struct fpga_dev *d = (struct fpga_dev *)file->private_data;
@ -224,37 +225,32 @@ long fpga_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
// register pid // register pid
case IOCTL_REGISTER_PID: case IOCTL_REGISTER_PID:
// read pid spin_lock(&pd->stat_lock);
ret_val = copy_from_user(&tmp, (unsigned long *)arg, sizeof(unsigned long));
if (ret_val != 0) { pid = current->pid;
pr_info("user data could not be coppied, return %d\n", ret_val);
cpid = (uint64_t)register_pid(d, pid);
if (cpid == -1)
{
dbg_info("registration failed pid %d\n", pid);
return -1;
} }
else {
spin_lock(&pd->stat_lock);
cpid = (uint64_t)register_pid(d, tmp[0]); // tmp[0] - pid dbg_info("registration succeeded pid %d, cpid %lld\n", pid, cpid);
if (cpid == -1)
{
dbg_info("registration failed pid %lld\n", tmp[0]);
return -1;
}
dbg_info("registration succeeded pid %lld, cpid %lld\n", tmp[0], cpid); tmp_cid = kzalloc(sizeof(struct cid_entry), GFP_KERNEL);
BUG_ON(!tmp_cid);
// inode tmp_cid->pid = pid;
tmp_cid = kzalloc(sizeof(struct cid_entry), GFP_KERNEL); tmp_cid->cpid = cpid;
BUG_ON(!tmp_cid);
tmp_cid->ino = file->f_path.dentry->d_inode->i_ino; hash_add(pid_cpid_map[d->id], &tmp_cid->entry, pid);
tmp_cid->cpid = cpid;
hash_add(cid_map[d->id], &tmp_cid->entry, tmp_cid->ino); // return cpid
ret_val = copy_to_user((unsigned long *)arg + 1, &cpid, sizeof(unsigned long));
// return cpid spin_unlock(&pd->stat_lock);
ret_val = copy_to_user((unsigned long *)arg + 1, &cpid, sizeof(unsigned long));
spin_unlock(&pd->stat_lock);
}
break; break;
// unregister pid // unregister pid
@ -266,16 +262,25 @@ long fpga_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
} }
else { else {
spin_lock(&pd->stat_lock); spin_lock(&pd->stat_lock);
cpid = tmp[0];
pid = d->pid_array[cpid];
ret_val = unregister_pid(d, tmp[0]); // tmp[0] - cpid ret_val = unregister_pid(d, cpid); // tmp[0] - cpid
if (ret_val == -1) { if (ret_val == -1) {
dbg_info("unregistration failed cpid %lld\n", tmp[0]); dbg_info("unregistration failed cpid %lld\n", cpid);
return -1; return -1;
} }
// inode // map
hash_for_each_possible(cid_map[d->id], tmp_cid, entry, file->f_path.dentry->d_inode->i_ino) { hash_for_each_possible(pid_cpid_map[d->id], tmp_cid, entry, pid) {
if(tmp_cid->ino == file->f_path.dentry->d_inode->i_ino && tmp_cid->cpid == tmp[0]) { if(tmp_cid->pid == pid && tmp_cid->cpid == cpid) {
// unamp all leftover user pages
tlb_put_user_pages_cpid(d, cpid, 1);
// unregister (if registered)
unregister_pid(d, cpid);
// Free from hash // Free from hash
hash_del(&tmp_cid->entry); hash_del(&tmp_cid->entry);
} }

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@ -173,9 +173,7 @@ ssize_t cyt_attr_nstats_q0_show(struct kobject *kobj, struct kobj_attribute *att
pr_info("coyote-sysfs: net stats QSFP0\n"); pr_info("coyote-sysfs: net stats QSFP0\n");
return sprintf(buf, "\n -- \033[31m\e[1mNET STATS\033[0m\e[0m QSFP0\n\n" return sprintf(buf, "\n -- \033[31m\e[1mNET STATS\033[0m\e[0m QSFP0\n\n"
"RX words: %lld\n"
"RX pkgs: %lld\n" "RX pkgs: %lld\n"
"TX words: %lld\n"
"TX pkgs: %lld\n" "TX pkgs: %lld\n"
"ARP RX pkgs: %lld\n" "ARP RX pkgs: %lld\n"
"ARP TX pkgs: %lld\n" "ARP TX pkgs: %lld\n"
@ -187,10 +185,10 @@ ssize_t cyt_attr_nstats_q0_show(struct kobject *kobj, struct kobj_attribute *att
"ROCE TX pkgs: %lld\n" "ROCE TX pkgs: %lld\n"
"IBV RX pkgs: %lld\n" "IBV RX pkgs: %lld\n"
"IBV TX pkgs: %lld\n" "IBV TX pkgs: %lld\n"
"CRC drop cnt: %lld\n"
"PSN drop cnt: %lld\n" "PSN drop cnt: %lld\n"
"Retrans cnt: %lld\n"
"TCP session cnt: %lld\n" "TCP session cnt: %lld\n"
"STRM down cnt: %lld\n\n", "STRM down: %lld\n\n",
LOW_32 (pd->fpga_stat_cnfg->net_0_debug[0]), LOW_32 (pd->fpga_stat_cnfg->net_0_debug[0]),
HIGH_32(pd->fpga_stat_cnfg->net_0_debug[0]), HIGH_32(pd->fpga_stat_cnfg->net_0_debug[0]),
@ -207,9 +205,7 @@ ssize_t cyt_attr_nstats_q0_show(struct kobject *kobj, struct kobj_attribute *att
LOW_32 (pd->fpga_stat_cnfg->net_0_debug[6]), LOW_32 (pd->fpga_stat_cnfg->net_0_debug[6]),
HIGH_32(pd->fpga_stat_cnfg->net_0_debug[6]), HIGH_32(pd->fpga_stat_cnfg->net_0_debug[6]),
LOW_32 (pd->fpga_stat_cnfg->net_0_debug[7]), LOW_32 (pd->fpga_stat_cnfg->net_0_debug[7]),
HIGH_32(pd->fpga_stat_cnfg->net_0_debug[7]), LOW_32 (pd->fpga_stat_cnfg->net_0_debug[8])
LOW_32 (pd->fpga_stat_cnfg->net_0_debug[8]),
LOW_32 (pd->fpga_stat_cnfg->net_0_debug[9])
); );
} }
@ -223,9 +219,7 @@ ssize_t cyt_attr_nstats_q1_show(struct kobject *kobj, struct kobj_attribute *att
pr_info("coyote-sysfs: net stats QSFP1\n"); pr_info("coyote-sysfs: net stats QSFP1\n");
return sprintf(buf, "\n -- \033[31m\e[1mNET STATS\033[0m\e[0m QSFP1\n\n" return sprintf(buf, "\n -- \033[31m\e[1mNET STATS\033[0m\e[0m QSFP1\n\n"
"RX words: %lld\n"
"RX pkgs: %lld\n" "RX pkgs: %lld\n"
"TX words: %lld\n"
"TX pkgs: %lld\n" "TX pkgs: %lld\n"
"ARP RX pkgs: %lld\n" "ARP RX pkgs: %lld\n"
"ARP TX pkgs: %lld\n" "ARP TX pkgs: %lld\n"
@ -237,10 +231,10 @@ ssize_t cyt_attr_nstats_q1_show(struct kobject *kobj, struct kobj_attribute *att
"ROCE TX pkgs: %lld\n" "ROCE TX pkgs: %lld\n"
"IBV RX pkgs: %lld\n" "IBV RX pkgs: %lld\n"
"IBV TX pkgs: %lld\n" "IBV TX pkgs: %lld\n"
"CRC drop cnt: %lld\n"
"PSN drop cnt: %lld\n" "PSN drop cnt: %lld\n"
"Retrans cnt: %lld\n"
"TCP session cnt: %lld\n" "TCP session cnt: %lld\n"
"STRM down cnt: %lld\n\n", "STRM down: %lld\n\n",
LOW_32 (pd->fpga_stat_cnfg->net_1_debug[0]), LOW_32 (pd->fpga_stat_cnfg->net_1_debug[0]),
HIGH_32(pd->fpga_stat_cnfg->net_1_debug[0]), HIGH_32(pd->fpga_stat_cnfg->net_1_debug[0]),
@ -257,9 +251,7 @@ ssize_t cyt_attr_nstats_q1_show(struct kobject *kobj, struct kobj_attribute *att
LOW_32 (pd->fpga_stat_cnfg->net_1_debug[6]), LOW_32 (pd->fpga_stat_cnfg->net_1_debug[6]),
HIGH_32(pd->fpga_stat_cnfg->net_1_debug[6]), HIGH_32(pd->fpga_stat_cnfg->net_1_debug[6]),
LOW_32 (pd->fpga_stat_cnfg->net_1_debug[7]), LOW_32 (pd->fpga_stat_cnfg->net_1_debug[7]),
HIGH_32(pd->fpga_stat_cnfg->net_1_debug[7]), LOW_32 (pd->fpga_stat_cnfg->net_1_debug[8])
LOW_32 (pd->fpga_stat_cnfg->net_1_debug[8]),
LOW_32 (pd->fpga_stat_cnfg->net_1_debug[9])
); );
} }

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@ -4,7 +4,11 @@
## General ## General
# Max supported regions (could be more if really needed with a bit of hacking) # Max supported regions
set(MULT_REGIONS 0)
if(N_REGIONS GREATER 1)
set(MULT_REGIONS 1)
endif()
if(N_REGIONS GREATER 15) if(N_REGIONS GREATER 15)
message(FATAL_ERROR "Max 15 regions supported.") message(FATAL_ERROR "Max 15 regions supported.")
endif() endif()
@ -165,6 +169,11 @@ if(DDR_AUTO)
endif() endif()
endif() endif()
set(MULT_DDR_CHAN 0)
if(N_DDR_CHAN GREATER 1)
set(MULT_DDR_CHAN 1)
endif()
# Compare for mismatch # Compare for mismatch
if(EN_DCARD) if(EN_DCARD)
MATH(EXPR N_DDRS "${DDR_0}+${DDR_1}+${DDR_2}+${DDR_3}") MATH(EXPR N_DDRS "${DDR_0}+${DDR_1}+${DDR_2}+${DDR_3}")
@ -231,9 +240,13 @@ endif()
# Channel designators # Channel designators
set(NN 0) set(NN 0)
set(MULT_STRM_AXI 0)
if(EN_STRM) if(EN_STRM)
set(STRM_CHAN ${NN}) set(STRM_CHAN ${NN})
MATH(EXPR NN "${NN}+1") MATH(EXPR NN "${NN}+1")
if(N_STRM_AXI GREATER 1)
set(MULT_STRM_AXI 1)
endif()
else() else()
set(STRM_CHAN -1) set(STRM_CHAN -1)
endif() endif()

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@ -42,9 +42,7 @@ module rdma_req_parser #(
input logic aresetn, input logic aresetn,
metaIntf.s s_req, metaIntf.s s_req,
metaIntf.m m_req, metaIntf.m m_req
output logic [31:0] used
); );
// FSM // FSM
@ -110,17 +108,7 @@ ila_req_parser inst_ila_parser (
); );
// Decoupling // Decoupling
axis_data_fifo_cnfg_rdma_512 inst_cmd_queue_in ( `META_ASSIGN(s_req, req_pre_parsed)
.s_axis_aresetn(aresetn),
.s_axis_aclk(aclk),
.s_axis_tvalid(s_req.valid),
.s_axis_tready(s_req.ready),
.s_axis_tdata(s_req.data),
.m_axis_tvalid(req_pre_parsed.valid),
.m_axis_tready(req_pre_parsed.ready),
.m_axis_tdata(req_pre_parsed.data),
.axis_wr_data_count(used)
);
logic [31:0] queue_used_out; logic [31:0] queue_used_out;
@ -275,6 +263,7 @@ always_comb begin: DP
req_parsed.data.last = plast_C; req_parsed.data.last = plast_C;
req_parsed.data.cmplt = cmplt_C; req_parsed.data.cmplt = cmplt_C;
req_parsed.data.ssn = ssn_C; req_parsed.data.ssn = ssn_C;
req_parsed.data.offs = 0;
req_parsed.data.msg[RDMA_LVADDR_OFFS+:RDMA_VADDR_BITS] = plvaddr_C; req_parsed.data.msg[RDMA_LVADDR_OFFS+:RDMA_VADDR_BITS] = plvaddr_C;
req_parsed.data.msg[RDMA_RVADDR_OFFS+:RDMA_VADDR_BITS] = prvaddr_C; req_parsed.data.msg[RDMA_RVADDR_OFFS+:RDMA_VADDR_BITS] = prvaddr_C;
req_parsed.data.msg[RDMA_LEN_OFFS+:RDMA_LEN_BITS] = plen_C; req_parsed.data.msg[RDMA_LEN_OFFS+:RDMA_LEN_BITS] = plen_C;

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@ -89,12 +89,11 @@ always_comb begin
rdma_sq_data[32+:RDMA_QPN_BITS] = rdma_sq.data.qpn; rdma_sq_data[32+:RDMA_QPN_BITS] = rdma_sq.data.qpn;
rdma_sq_data[32+RDMA_QPN_BITS+0+:1] = rdma_sq.data.host; rdma_sq_data[32+RDMA_QPN_BITS+0+:1] = rdma_sq.data.host;
rdma_sq_data[32+RDMA_QPN_BITS+2+:1] = rdma_sq.data.last; rdma_sq_data[32+RDMA_QPN_BITS+1+:1] = rdma_sq.data.last;
rdma_sq_data[32+RDMA_QPN_BITS+4+:RDMA_MSN_BITS] = rdma_sq.data.ssn; rdma_sq_data[32+RDMA_QPN_BITS+2+:RDMA_OFFS_BITS] = rdma_sq.data.offs;
rdma_sq_data[32+RDMA_QPN_BITS+4+RDMA_MSN_BITS+:RDMA_OFFS_BITS] = rdma_sq.data.offs;
rdma_sq_data[32+RDMA_QPN_BITS+4+RDMA_MSN_BITS+RDMA_OFFS_BITS+:RDMA_MSG_BITS] = rdma_sq.data.msg; rdma_sq_data[32+RDMA_QPN_BITS+2+RDMA_OFFS_BITS+:RDMA_MSG_BITS] = rdma_sq.data.msg;
`else `else
rdma_sq_data = 0; rdma_sq_data = 0;

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@ -82,7 +82,7 @@ if(ENABLED == 1) begin
// Crossings // Crossings
// //
axis_data_fifo_net_ccross_512 inst_cross_ns_nr ( axis_data_fifo_net_ccross_early_512 inst_cross_ns_nr (
.m_axis_aclk(rclk), .m_axis_aclk(rclk),
.s_axis_aclk(nclk), .s_axis_aclk(nclk),
.s_axis_aresetn(nresetn_reg), .s_axis_aresetn(nresetn_reg),
@ -98,7 +98,7 @@ if(ENABLED == 1) begin
.m_axis_tlast(m_axis_rclk_int.tlast) .m_axis_tlast(m_axis_rclk_int.tlast)
); );
axis_data_fifo_net_ccross_512 inst_cross_nr_ns ( axis_data_fifo_net_ccross_early_512 inst_cross_nr_ns (
.m_axis_aclk(nclk), .m_axis_aclk(nclk),
.s_axis_aclk(rclk), .s_axis_aclk(rclk),
.s_axis_aresetn(rresetn_reg), .s_axis_aresetn(rresetn_reg),

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@ -139,7 +139,7 @@ if(ENABLED == 1) begin
`ifdef EN_STATS `ifdef EN_STATS
// Stats // Stats
axis_clock_converter_net_608 inst_ccross_qp_interface ( axis_clock_converter_net_512 inst_ccross_qp_interface (
.s_axis_aresetn(nresetn), .s_axis_aresetn(nresetn),
.m_axis_aresetn(aresetn), .m_axis_aresetn(aresetn),
.s_axis_aclk(nclk), .s_axis_aclk(nclk),
@ -255,7 +255,7 @@ else begin
`ifdef EN_STATS `ifdef EN_STATS
// Stats // Stats
axis_register_slice_net_608 inst_reg_net_stats ( axis_register_slice_net_512 inst_reg_net_stats (
.aclk(aclk), .aclk(aclk),
.aresetn(aresetn), .aresetn(aresetn),
.s_axis_tvalid(1'b1), .s_axis_tvalid(1'b1),

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@ -120,7 +120,7 @@ module network_slice (
`ifdef EN_STATS `ifdef EN_STATS
// Stats // Stats
axis_register_slice_net_608 inst_reg_net_stats ( axis_register_slice_net_512 inst_reg_net_stats (
.aclk(aclk), .aclk(aclk),
.aresetn(aresetn), .aresetn(aresetn),
.s_axis_tvalid(1'b1), .s_axis_tvalid(1'b1),

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@ -161,7 +161,7 @@ for(genvar i = 0; i < N_STAGES; i++) begin
`ifdef EN_STATS `ifdef EN_STATS
// ARP reply // ARP reply
axis_register_slice_net_608 ( axis_register_slice_net_512 (
.aclk(aclk), .aclk(aclk),
.aresetn(aresetn), .aresetn(aresetn),
.s_axis_tvalid(1'b1), .s_axis_tvalid(1'b1),

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@ -860,13 +860,12 @@ end
logic[31:0] roce_tx_pkg_counter; logic[31:0] roce_tx_pkg_counter;
logic[31:0] roce_retrans_counter; logic[31:0] roce_retrans_counter;
logic[31:0] axis_stream_down_counter; logic[15:0] axis_stream_down_counter;
logic axis_stream_down;
net_stat_t[NET_STATS_DELAY-1:0] net_stats_tmp; // Slice net_stat_t[NET_STATS_DELAY-1:0] net_stats_tmp; // Slice
assign net_stats_tmp[0].rx_word_counter = rx_word_counter;
assign net_stats_tmp[0].rx_pkg_counter = rx_pkg_counter; assign net_stats_tmp[0].rx_pkg_counter = rx_pkg_counter;
assign net_stats_tmp[0].tx_word_counter = tx_word_counter;
assign net_stats_tmp[0].tx_pkg_counter = tx_pkg_counter; assign net_stats_tmp[0].tx_pkg_counter = tx_pkg_counter;
assign net_stats_tmp[0].arp_rx_pkg_counter = arp_rx_pkg_counter; assign net_stats_tmp[0].arp_rx_pkg_counter = arp_rx_pkg_counter;
assign net_stats_tmp[0].arp_tx_pkg_counter = arp_tx_pkg_counter; assign net_stats_tmp[0].arp_tx_pkg_counter = arp_tx_pkg_counter;
@ -874,15 +873,14 @@ end
assign net_stats_tmp[0].icmp_tx_pkg_counter = icmp_tx_pkg_counter; assign net_stats_tmp[0].icmp_tx_pkg_counter = icmp_tx_pkg_counter;
assign net_stats_tmp[0].tcp_rx_pkg_counter = tcp_rx_pkg_counter; assign net_stats_tmp[0].tcp_rx_pkg_counter = tcp_rx_pkg_counter;
assign net_stats_tmp[0].tcp_tx_pkg_counter = tcp_tx_pkg_counter; assign net_stats_tmp[0].tcp_tx_pkg_counter = tcp_tx_pkg_counter;
assign net_stats_tmp[0].tcp_session_counter = session_count_data;
assign net_stats_tmp[0].roce_rx_pkg_counter = roce_rx_pkg_counter; assign net_stats_tmp[0].roce_rx_pkg_counter = roce_rx_pkg_counter;
assign net_stats_tmp[0].roce_tx_pkg_counter = roce_tx_pkg_counter; assign net_stats_tmp[0].roce_tx_pkg_counter = roce_tx_pkg_counter;
assign net_stats_tmp[0].ibv_rx_pkg_counter = regIbvRxPkgCount; assign net_stats_tmp[0].ibv_rx_pkg_counter = regIbvRxPkgCount;
assign net_stats_tmp[0].ibv_tx_pkg_counter = regIbvTxPkgCount; assign net_stats_tmp[0].ibv_tx_pkg_counter = regIbvTxPkgCount;
assign net_stats_tmp[0].roce_crc_drop_counter = regCrcDropPkgCount;
assign net_stats_tmp[0].roce_psn_drop_counter = regInvalidPsnDropCount; assign net_stats_tmp[0].roce_psn_drop_counter = regInvalidPsnDropCount;
assign net_stats_tmp[0].roce_retrans_counter = regRetransCount; assign net_stats_tmp[0].roce_retrans_counter = regRetransCount;
assign net_stats_tmp[0].axis_stream_down_counter = axis_stream_down_counter; assign net_stats_tmp[0].tcp_session_counter = session_count_data;
assign net_stats_tmp[0].axis_stream_down = axis_stream_down;
assign m_net_stats = net_stats_tmp[NET_STATS_DELAY-1]; assign m_net_stats = net_stats_tmp[NET_STATS_DELAY-1];
@ -904,6 +902,7 @@ end
roce_tx_pkg_counter <= '0; roce_tx_pkg_counter <= '0;
axis_stream_down_counter <= '0; axis_stream_down_counter <= '0;
axis_stream_down <= 1'b0;
end end
// Reg the stats // Reg the stats
@ -978,8 +977,9 @@ end
axis_stream_down_counter <= '0; axis_stream_down_counter <= '0;
end end
if (s_axis_net.tvalid && ~s_axis_net.tready) begin if (s_axis_net.tvalid && ~s_axis_net.tready) begin
axis_stream_down_counter <= axis_stream_down_counter + 1; axis_stream_down_counter <= (axis_stream_down_counter == NET_STRM_DOWN_THRS) ? axis_stream_down_counter : axis_stream_down_counter + 1;
end end
axis_stream_down <= (axis_stream_down_counter == NET_STRM_DOWN_THRS);
end end

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@ -145,7 +145,7 @@ module static_slave (
// ------------------------------------------------------------------ // ------------------------------------------------------------------
// Constants // Constants
localparam integer N_REGS = 128; localparam integer N_REGS = 160;
localparam integer ADDR_LSB = $clog2(AXIL_DATA_BITS/8); localparam integer ADDR_LSB = $clog2(AXIL_DATA_BITS/8);
localparam integer ADDR_MSB = $clog2(N_REGS); localparam integer ADDR_MSB = $clog2(N_REGS);
localparam integer AXIL_ADDR_BITS = ADDR_LSB + ADDR_MSB; localparam integer AXIL_ADDR_BITS = ADDR_LSB + ADDR_MSB;
@ -316,28 +316,27 @@ localparam integer XDMA_STAT_2_AXIS = 72;
localparam integer XDMA_STAT_3_BPSS = 73; localparam integer XDMA_STAT_3_BPSS = 73;
localparam integer XDMA_STAT_3_CMPL = 74; localparam integer XDMA_STAT_3_CMPL = 74;
localparam integer XDMA_STAT_3_AXIS = 75; localparam integer XDMA_STAT_3_AXIS = 75;
// NET STATS
localparam integer NET_STAT_0_RX_REG = 96;
localparam integer NET_STAT_0_TX_REG = 97;
localparam integer NET_STAT_0_ARP_REG = 98;
localparam integer NET_STAT_0_ICMP_REG = 99;
localparam integer NET_STAT_0_TCP_REG = 100;
localparam integer NET_STAT_0_RDMA_REG = 101;
localparam integer NET_STAT_0_IBV_REG = 102;
localparam integer NET_STAT_0_DROP_REG = 103;
localparam integer NET_STAT_0_SESS_REG = 104;
localparam integer NET_STAT_0_DOWN_REG = 105;
localparam integer NET_STAT_1_RX_REG = 112; // NET STATS
localparam integer NET_STAT_1_TX_REG = 113; localparam integer NET_STAT_0_PKG_REG = 96;
localparam integer NET_STAT_1_ARP_REG = 114; localparam integer NET_STAT_0_ARP_REG = 97;
localparam integer NET_STAT_1_ICMP_REG = 115; localparam integer NET_STAT_0_ICMP_REG = 98;
localparam integer NET_STAT_1_TCP_REG = 116; localparam integer NET_STAT_0_TCP_REG = 99;
localparam integer NET_STAT_1_RDMA_REG = 117; localparam integer NET_STAT_0_RDMA_REG = 100;
localparam integer NET_STAT_1_IBV_REG = 118; localparam integer NET_STAT_0_IBV_REG = 101;
localparam integer NET_STAT_1_DROP_REG = 119; localparam integer NET_STAT_0_DROP_REG = 102;
localparam integer NET_STAT_1_SESS_REG = 120; localparam integer NET_STAT_0_SESS_REG = 103;
localparam integer NET_STAT_1_DOWN_REG = 121; localparam integer NET_STAT_0_DOWN_REG = 104;
localparam integer NET_STAT_1_PKG_REG = 128;
localparam integer NET_STAT_1_ARP_REG = 129;
localparam integer NET_STAT_1_ICMP_REG = 130;
localparam integer NET_STAT_1_TCP_REG = 131;
localparam integer NET_STAT_1_RDMA_REG = 132;
localparam integer NET_STAT_1_IBV_REG = 133;
localparam integer NET_STAT_1_DROP_REG = 134;
localparam integer NET_STAT_1_SESS_REG = 135;
localparam integer NET_STAT_1_DOWN_REG = 136;
// ---------------------------------------------------------------------------------------- // ----------------------------------------------------------------------------------------
// Write process // Write process
@ -883,10 +882,8 @@ always_ff @(posedge aclk) begin
`endif `endif
`ifdef EN_NET_0 `ifdef EN_NET_0
NET_STAT_0_RX_REG: // rx NET_STAT_0_PKG_REG: // rx and tx
axi_rdata <= {s_net_stats_0.rx_pkg_counter, s_net_stats_0.rx_word_counter}; axi_rdata <= {s_net_stats_0.tx_pkg_counter, s_net_stats_0.rx_pkg_counter};
NET_STAT_0_TX_REG: // tx
axi_rdata <= {s_net_stats_0.tx_pkg_counter, s_net_stats_0.tx_word_counter};
NET_STAT_0_ARP_REG: // arp NET_STAT_0_ARP_REG: // arp
axi_rdata <= {s_net_stats_0.arp_tx_pkg_counter, s_net_stats_0.arp_rx_pkg_counter}; axi_rdata <= {s_net_stats_0.arp_tx_pkg_counter, s_net_stats_0.arp_rx_pkg_counter};
NET_STAT_0_ICMP_REG: // icmp NET_STAT_0_ICMP_REG: // icmp
@ -898,18 +895,16 @@ always_ff @(posedge aclk) begin
NET_STAT_0_IBV_REG: // ibv NET_STAT_0_IBV_REG: // ibv
axi_rdata <= {s_net_stats_0.ibv_tx_pkg_counter, s_net_stats_0.ibv_rx_pkg_counter}; axi_rdata <= {s_net_stats_0.ibv_tx_pkg_counter, s_net_stats_0.ibv_rx_pkg_counter};
NET_STAT_0_DROP_REG: // rdma drop NET_STAT_0_DROP_REG: // rdma drop
axi_rdata <= {s_net_stats_0.roce_psn_drop_counter, s_net_stats_0.roce_crc_drop_counter}; axi_rdata <= {s_net_stats_0.roce_retrans_counter, s_net_stats_0.roce_psn_drop_counter};
NET_STAT_0_SESS_REG: // tcp sessions NET_STAT_0_SESS_REG: // tcp sessions
axi_rdata[31:0] <= s_net_stats_0.tcp_session_counter; axi_rdata[31:0] <= s_net_stats_0.tcp_session_counter;
NET_STAT_0_DOWN_REG: // rdma NET_STAT_0_DOWN_REG: // rdma
axi_rdata <= {s_net_stats_0.roce_retrans_counter, s_net_stats_0.axis_stream_down_counter}; axi_rdata[0] <= s_net_stats_0.axis_stream_down;
`endif `endif
`ifdef EN_NET_1 `ifdef EN_NET_1
NET_STAT_1_RX_REG: // rx NET_STAT_1_PKG_REG: // rx and tx
axi_rdata <= {s_net_stats_1.rx_pkg_counter, s_net_stats_1.rx_word_counter}; axi_rdata <= {s_net_stats_1.tx_pkg_counter, s_net_stats_1.rx_pkg_counter};
NET_STAT_1_TX_REG: // tx
axi_rdata <= {s_net_stats_1.tx_pkg_counter, s_net_stats_1.tx_word_counter};
NET_STAT_1_ARP_REG: // arp NET_STAT_1_ARP_REG: // arp
axi_rdata <= {s_net_stats_1.arp_tx_pkg_counter, s_net_stats_1.arp_rx_pkg_counter}; axi_rdata <= {s_net_stats_1.arp_tx_pkg_counter, s_net_stats_1.arp_rx_pkg_counter};
NET_STAT_1_ICMP_REG: // icmp NET_STAT_1_ICMP_REG: // icmp
@ -921,11 +916,11 @@ always_ff @(posedge aclk) begin
NET_STAT_1_IBV_REG: // ibv NET_STAT_1_IBV_REG: // ibv
axi_rdata <= {s_net_stats_1.ibv_tx_pkg_counter, s_net_stats_1.ibv_rx_pkg_counter}; axi_rdata <= {s_net_stats_1.ibv_tx_pkg_counter, s_net_stats_1.ibv_rx_pkg_counter};
NET_STAT_1_DROP_REG: // rdma drop NET_STAT_1_DROP_REG: // rdma drop
axi_rdata <= {s_net_stats_1.roce_psn_drop_counter, s_net_stats_1.roce_crc_drop_counter}; axi_rdata <= {s_net_stats_1.roce_retrans_counter, s_net_stats_1.roce_psn_drop_counter};
NET_STAT_1_SESS_REG: // tcp sessions NET_STAT_1_SESS_REG: // tcp sessions
axi_rdata[31:0] <= s_net_stats_1.tcp_session_counter; axi_rdata[31:0] <= s_net_stats_1.tcp_session_counter;
NET_STAT_1_DOWN_REG: // rdma NET_STAT_1_DOWN_REG: // rdma
axi_rdata <= {s_net_stats_1.roce_retrans_counter, s_net_stats_1.axis_stream_down_counter}; axi_rdata[0] <= s_net_stats_1.axis_stream_down;
`endif `endif
`endif `endif

View File

@ -98,6 +98,10 @@ if {$cfg(en_rdma) eq 1} {
create_ip -name rocev2 -vendor ethz.systems.fpga -library hls -version 0.82 -module_name rocev2_ip create_ip -name rocev2 -vendor ethz.systems.fpga -library hls -version 0.82 -module_name rocev2_ip
} }
# Cmd
create_ip -name axis_data_fifo -vendor xilinx.com -library ip -version 2.0 -module_name axis_data_fifo_req_512_used
set_property -dict [list CONFIG.TDATA_NUM_BYTES {64} CONFIG.FIFO_DEPTH {32} CONFIG.HAS_WR_DATA_COUNT {1} ] [get_ips axis_data_fifo_req_512_used]
## Crossings ## Crossings
create_ip -name axis_clock_converter -vendor xilinx.com -library ip -version 1.1 -module_name axis_clock_converter_rdma_16 create_ip -name axis_clock_converter -vendor xilinx.com -library ip -version 1.1 -module_name axis_clock_converter_rdma_16
set_property -dict [list CONFIG.TDATA_NUM_BYTES {2} CONFIG.SYNCHRONIZATION_STAGES {4} ] [get_ips axis_clock_converter_rdma_16] set_property -dict [list CONFIG.TDATA_NUM_BYTES {2} CONFIG.SYNCHRONIZATION_STAGES {4} ] [get_ips axis_clock_converter_rdma_16]
@ -433,8 +437,8 @@ set_property -dict [list CONFIG.AXI_ADDR_WIDTH {64} CONFIG.INTERCONNECT_DATA_WID
## Network top ## Network top
## ##
create_ip -name axis_data_fifo -vendor xilinx.com -library ip -version 2.0 -module_name axis_data_fifo_net_ccross_512 create_ip -name axis_data_fifo -vendor xilinx.com -library ip -version 2.0 -module_name axis_data_fifo_net_ccross_early_512
set_property -dict [list CONFIG.TDATA_NUM_BYTES {64} CONFIG.IS_ACLK_ASYNC {1} CONFIG.FIFO_DEPTH {512} CONFIG.HAS_TKEEP {1} CONFIG.HAS_TLAST {1} ] [get_ips axis_data_fifo_net_ccross_512] set_property -dict [list CONFIG.TDATA_NUM_BYTES {64} CONFIG.IS_ACLK_ASYNC {1} CONFIG.FIFO_DEPTH {512} CONFIG.HAS_TKEEP {1} CONFIG.HAS_TLAST {1} ] [get_ips axis_data_fifo_net_ccross_early_512]
## Crossings ## Crossings
create_ip -name axis_clock_converter -vendor xilinx.com -library ip -version 1.1 -module_name axis_clock_converter_net_8 create_ip -name axis_clock_converter -vendor xilinx.com -library ip -version 1.1 -module_name axis_clock_converter_net_8
@ -449,8 +453,8 @@ set_property -dict [list CONFIG.TDATA_NUM_BYTES {6} CONFIG.SYNCHRONIZATION_STAGE
create_ip -name axis_clock_converter -vendor xilinx.com -library ip -version 1.1 -module_name axis_clock_converter_net_56 create_ip -name axis_clock_converter -vendor xilinx.com -library ip -version 1.1 -module_name axis_clock_converter_net_56
set_property -dict [list CONFIG.TDATA_NUM_BYTES {7} CONFIG.SYNCHRONIZATION_STAGES {4} ] [get_ips axis_clock_converter_net_56] set_property -dict [list CONFIG.TDATA_NUM_BYTES {7} CONFIG.SYNCHRONIZATION_STAGES {4} ] [get_ips axis_clock_converter_net_56]
create_ip -name axis_clock_converter -vendor xilinx.com -library ip -version 1.1 -module_name axis_clock_converter_net_608 create_ip -name axis_clock_converter -vendor xilinx.com -library ip -version 1.1 -module_name axis_clock_converter_net_512
set_property -dict [list CONFIG.TDATA_NUM_BYTES {76} CONFIG.SYNCHRONIZATION_STAGES {4} ] [get_ips axis_clock_converter_net_608] set_property -dict [list CONFIG.TDATA_NUM_BYTES {64} CONFIG.SYNCHRONIZATION_STAGES {4} ] [get_ips axis_clock_converter_net_512]
## Crossings FIFO ## Crossings FIFO
create_ip -name axis_data_fifo -vendor xilinx.com -library ip -version 2.0 -module_name axis_data_fifo_net_ccross_8 create_ip -name axis_data_fifo -vendor xilinx.com -library ip -version 2.0 -module_name axis_data_fifo_net_ccross_8
@ -465,8 +469,8 @@ set_property -dict [list CONFIG.TDATA_NUM_BYTES {6} CONFIG.IS_ACLK_ASYNC {1} CON
create_ip -name axis_data_fifo -vendor xilinx.com -library ip -version 2.0 -module_name axis_data_fifo_net_ccross_56 create_ip -name axis_data_fifo -vendor xilinx.com -library ip -version 2.0 -module_name axis_data_fifo_net_ccross_56
set_property -dict [list CONFIG.TDATA_NUM_BYTES {7} CONFIG.IS_ACLK_ASYNC {1} CONFIG.FIFO_DEPTH {32} ] [get_ips axis_data_fifo_net_ccross_56] set_property -dict [list CONFIG.TDATA_NUM_BYTES {7} CONFIG.IS_ACLK_ASYNC {1} CONFIG.FIFO_DEPTH {32} ] [get_ips axis_data_fifo_net_ccross_56]
create_ip -name axis_data_fifo -vendor xilinx.com -library ip -version 2.0 -module_name axis_data_fifo_net_ccross_608 create_ip -name axis_data_fifo -vendor xilinx.com -library ip -version 2.0 -module_name axis_data_fifo_net_ccross_512
set_property -dict [list CONFIG.TDATA_NUM_BYTES {76} CONFIG.IS_ACLK_ASYNC {1} CONFIG.FIFO_DEPTH {32} ] [get_ips axis_data_fifo_net_ccross_608] set_property -dict [list CONFIG.TDATA_NUM_BYTES {64} CONFIG.IS_ACLK_ASYNC {1} CONFIG.FIFO_DEPTH {32} ] [get_ips axis_data_fifo_net_ccross_512]
## Slicing ## Slicing
create_ip -name axis_register_slice -vendor xilinx.com -library ip -version 1.1 -module_name axis_register_slice_net_8 create_ip -name axis_register_slice -vendor xilinx.com -library ip -version 1.1 -module_name axis_register_slice_net_8
@ -481,8 +485,8 @@ set_property -dict [list CONFIG.TDATA_NUM_BYTES {6} CONFIG.REG_CONFIG {8} ] [get
create_ip -name axis_register_slice -vendor xilinx.com -library ip -version 1.1 -module_name axis_register_slice_net_56 create_ip -name axis_register_slice -vendor xilinx.com -library ip -version 1.1 -module_name axis_register_slice_net_56
set_property -dict [list CONFIG.TDATA_NUM_BYTES {7} CONFIG.REG_CONFIG {8} ] [get_ips axis_register_slice_net_56] set_property -dict [list CONFIG.TDATA_NUM_BYTES {7} CONFIG.REG_CONFIG {8} ] [get_ips axis_register_slice_net_56]
create_ip -name axis_register_slice -vendor xilinx.com -library ip -version 1.1 -module_name axis_register_slice_net_608 create_ip -name axis_register_slice -vendor xilinx.com -library ip -version 1.1 -module_name axis_register_slice_net_512
set_property -dict [list CONFIG.TDATA_NUM_BYTES {76} CONFIG.REG_CONFIG {8} ] [get_ips axis_register_slice_net_608] set_property -dict [list CONFIG.TDATA_NUM_BYTES {64} CONFIG.REG_CONFIG {8} ] [get_ips axis_register_slice_net_512]
## Buffering ## Buffering
create_ip -name axis_data_fifo -vendor xilinx.com -library ip -version 2.0 -module_name axis_data_fifo_net_8 create_ip -name axis_data_fifo -vendor xilinx.com -library ip -version 2.0 -module_name axis_data_fifo_net_8
@ -497,8 +501,8 @@ set_property -dict [list CONFIG.TDATA_NUM_BYTES {6} CONFIG.FIFO_DEPTH {32} ] [ge
create_ip -name axis_data_fifo -vendor xilinx.com -library ip -version 2.0 -module_name axis_data_fifo_net_56 create_ip -name axis_data_fifo -vendor xilinx.com -library ip -version 2.0 -module_name axis_data_fifo_net_56
set_property -dict [list CONFIG.TDATA_NUM_BYTES {7} CONFIG.FIFO_DEPTH {32} ] [get_ips axis_data_fifo_net_56] set_property -dict [list CONFIG.TDATA_NUM_BYTES {7} CONFIG.FIFO_DEPTH {32} ] [get_ips axis_data_fifo_net_56]
create_ip -name axis_data_fifo -vendor xilinx.com -library ip -version 2.0 -module_name axis_data_fifo_net_608 create_ip -name axis_data_fifo -vendor xilinx.com -library ip -version 2.0 -module_name axis_data_fifo_net_512
set_property -dict [list CONFIG.TDATA_NUM_BYTES {76} CONFIG.FIFO_DEPTH {32} ] [get_ips axis_data_fifo_net_608] set_property -dict [list CONFIG.TDATA_NUM_BYTES {64} CONFIG.FIFO_DEPTH {32} ] [get_ips axis_data_fifo_net_512]
## ##
## Network stack ## Network stack

View File

@ -52,12 +52,6 @@
{% if cnfg.en_net %} {% if cnfg.en_net %}
`define EN_NET `define EN_NET
{% endif %} {% endif %}
{% if cnfg.mult_regions %}
`define MULT_REGIONS
{% endif %}
{% if cnfg.mult_ddr_chan %}
`define MULT_DDR_CHAN
{% endif %}
{% if cnfg.en_aclk %} {% if cnfg.en_aclk %}
`define EN_ACLK `define EN_ACLK
{% endif %} {% endif %}
@ -97,9 +91,15 @@
{% if cnfg.vit_hls %} {% if cnfg.vit_hls %}
`define VITIS_HLS `define VITIS_HLS
{% endif %} {% endif %}
{% if cnfg.mult_regions %}
`define MULT_REGIONS
{% endif %}
{% if cnfg.mult_strm_axi %} {% if cnfg.mult_strm_axi %}
`define MULT_STRM_AXI `define MULT_STRM_AXI
{% endif %} {% endif %}
{% if cnfg.mult_ddr_chan %}
`define MULT_DDR_CHAN
{% endif %}
package lynxTypes; package lynxTypes;
@ -188,6 +188,7 @@ package lynxTypes;
parameter integer MAC_ADDR_BITS = 48; parameter integer MAC_ADDR_BITS = 48;
parameter integer DEF_MAC_ADDRESS = 48'hE59D02350A00; // LSB first, 00:0A:35:02:9D:E5 parameter integer DEF_MAC_ADDRESS = 48'hE59D02350A00; // LSB first, 00:0A:35:02:9D:E5
parameter integer DEF_IP_ADDRESS = 32'hD1D4010B; // LSB first, 0B:01:D4:D1 parameter integer DEF_IP_ADDRESS = 32'hD1D4010B; // LSB first, 0B:01:D4:D1
parameter integer NET_STRM_DOWN_THRS = 256;
// Network RDMA // Network RDMA
parameter integer APP_READ = 0; parameter integer APP_READ = 0;
@ -195,6 +196,9 @@ package lynxTypes;
parameter integer APP_SEND = 2; parameter integer APP_SEND = 2;
parameter integer APP_IMMED = 3; parameter integer APP_IMMED = 3;
parameter integer RC_SEND_FIRST = 5'h0;
parameter integer RC_SEND_MIDDLE = 5'h1;
parameter integer RC_SEND_LAST = 5'h2;
parameter integer RC_SEND_ONLY = 5'h4; parameter integer RC_SEND_ONLY = 5'h4;
parameter integer RC_RDMA_WRITE_FIRST = 5'h6; parameter integer RC_RDMA_WRITE_FIRST = 5'h6;
parameter integer RC_RDMA_WRITE_MIDDLE = 5'h7; parameter integer RC_RDMA_WRITE_MIDDLE = 5'h7;
@ -229,6 +233,7 @@ package lynxTypes;
parameter integer RDMA_LEN_OFFS = 2*RDMA_VADDR_BITS; parameter integer RDMA_LEN_OFFS = 2*RDMA_VADDR_BITS;
parameter integer RDMA_PARAMS_OFFS = 2*RDMA_VADDR_BITS + RDMA_LEN_BITS; parameter integer RDMA_PARAMS_OFFS = 2*RDMA_VADDR_BITS + RDMA_LEN_BITS;
parameter integer RDMA_MSN_BITS = 24; parameter integer RDMA_MSN_BITS = 24;
parameter integer RDMA_OFFS_BITS = 4;
parameter integer RDMA_SNDRM_BITS = 8; parameter integer RDMA_SNDRM_BITS = 8;
parameter integer RDMA_MAX_OUTSTANDING = 32; parameter integer RDMA_MAX_OUTSTANDING = 32;
parameter integer RDMA_MODE_PARSE = 0; parameter integer RDMA_MODE_PARSE = 0;
@ -374,15 +379,19 @@ package lynxTypes;
logic host; logic host;
logic mode; logic mode;
logic last; logic last;
logic cmplt;
logic [RDMA_MSN_BITS-1:0] ssn;
logic [RDMA_OFFS_BITS-1:0] offs;
logic [RDMA_MSG_BITS-1:0] msg; logic [RDMA_MSG_BITS-1:0] msg;
logic [RDMA_REQ_BITS-RDMA_MSG_BITS-3-RDMA_QPN_BITS-RDMA_OPCODE_BITS-1:0] rsrvd; logic [RDMA_REQ_BITS-RDMA_MSG_BITS-3-RDMA_QPN_BITS-RDMA_OPCODE_BITS-1:0] rsrvd;
} rdma_req_t; } rdma_req_t;
typedef struct packed { typedef struct packed {
logic rd; logic rd;
logic cmplt;
logic [PID_BITS-1:0] pid; logic [PID_BITS-1:0] pid;
logic [DEST_BITS-1:0] vfid; logic [DEST_BITS-1:0] vfid;
logic [RDMA_ACK_MSN_BITS-1:0] psn; logic [RDMA_ACK_MSN_BITS-1:0] ssn;
} rdma_ack_t; } rdma_ack_t;
typedef struct packed { typedef struct packed {
@ -450,9 +459,7 @@ package lynxTypes;
} xdma_stat_t; } xdma_stat_t;
typedef struct packed { typedef struct packed {
logic [31:0] rx_word_counter;
logic [31:0] rx_pkg_counter; logic [31:0] rx_pkg_counter;
logic [31:0] tx_word_counter;
logic [31:0] tx_pkg_counter; logic [31:0] tx_pkg_counter;
logic [31:0] arp_rx_pkg_counter; logic [31:0] arp_rx_pkg_counter;
logic [31:0] arp_tx_pkg_counter; logic [31:0] arp_tx_pkg_counter;
@ -464,10 +471,9 @@ package lynxTypes;
logic [31:0] roce_tx_pkg_counter; logic [31:0] roce_tx_pkg_counter;
logic [31:0] ibv_rx_pkg_counter; logic [31:0] ibv_rx_pkg_counter;
logic [31:0] ibv_tx_pkg_counter; logic [31:0] ibv_tx_pkg_counter;
logic [31:0] roce_crc_drop_counter;
logic [31:0] roce_psn_drop_counter; logic [31:0] roce_psn_drop_counter;
logic [31:0] roce_retrans_counter;
logic [15:0] tcp_session_counter; logic [15:0] tcp_session_counter;
logic [7:0] axis_stream_down_counter;
logic axis_stream_down; logic axis_stream_down;
} net_stat_t; } net_stat_t;