replica
/
Coyote
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

fix HBM dual bank inst.

This commit is contained in:
d-kor 2022-11-10 10:20:29 +01:00
parent 181a11bc2e
commit 61c1ba4c02
3 changed files with 19 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
hw/hdl/slave/cnfg_slave_avx.sv
View File

@ -888,7 +888,7 @@ assign wr_req_host.ready = m_wr_req.ready;
// RDMA requests
metaIntf #(.STYPE(rdma_req_t)) rdma_0_sq_cnfg();
metaIntf #(.STYPE(rdma_req_t)) rdma_0_sq;
metaIntf #(.STYPE(rdma_req_t)) rdma_0_sq();
// Assign
assign rdma_0_sq_cnfg.data.opcode = slv_reg[RDMA_0_POST_REG][1+:RDMA_OPCODE_BITS]; // opcode

11
hw/scripts/bd/cr_hbm.tcl
View File

@ -259,7 +259,7 @@ proc cr_bd_design_hbm { parentCell } {
for {set i 0} {$i < 32 - $cnfg(n_mem_chan)} {incr i} {
set cmd "set axi_toff_in_$i \[ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 axi_toff_in_$i ]
set_property -dict \[ list \
CONFIG.ADDR_WIDTH {33} \
CONFIG.ADDR_WIDTH {64} \
CONFIG.ARUSER_WIDTH {0} \
CONFIG.AWUSER_WIDTH {0} \
CONFIG.BUSER_WIDTH {0} \
@ -364,6 +364,13 @@ proc cr_bd_design_hbm { parentCell } {
] $axi_apb_bridge_inst
# Create instance: hbm_inst, and set properties
# Set density first
if($cnfg(hbm_size) == 33) {
set hbm_density "8GB"
} else {
set hbm_density "16GB"
}
set cmd "set hbm_inst \[ create_bd_cell -type ip -vlnv xilinx.com:ip:hbm:1.0 hbm_inst ]
set_property -dict \[ list \
CONFIG.USER_AXI_CLK_FREQ {[expr {$cnfg(hclk_f)}]} \
@ -371,7 +378,7 @@ proc cr_bd_design_hbm { parentCell } {
CONFIG.USER_CLK_SEL_LIST0 {AXI_15_ACLK} \
CONFIG.USER_CLK_SEL_LIST1 {AXI_31_ACLK} \
CONFIG.USER_DIS_REF_CLK_BUFG {TRUE} \
CONFIG.USER_HBM_DENSITY {8GB} \
CONFIG.USER_HBM_DENSITY {$hbm_density} \
CONFIG.USER_HBM_STACK {2} \
CONFIG.USER_INIT_TIMEOUT_VAL {0} \
CONFIG.USER_MC0_ECC_SCRUB_PERIOD {0x0032} \

11
hw/scripts/bd/cr_hbm_split.tcl
View File

@ -257,7 +257,7 @@ proc cr_bd_design_hbm { parentCell } {
for {set i 0} {$i < 2 * (16 - $cnfg(n_mem_chan))} {incr i} {
set cmd "set axi_toff_in_$i \[ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 axi_toff_in_$i ]
set_property -dict \[ list \
CONFIG.ADDR_WIDTH {33} \
CONFIG.ADDR_WIDTH {64} \
CONFIG.ARUSER_WIDTH {0} \
CONFIG.AWUSER_WIDTH {0} \
CONFIG.BUSER_WIDTH {0} \
@ -356,6 +356,13 @@ proc cr_bd_design_hbm { parentCell } {
] $axi_apb_bridge_inst
# Create instance: hbm_inst, and set properties
# Set density first
if($cnfg(hbm_size) == 33) {
set hbm_density "8GB"
} else {
set hbm_density "16GB"
}
set cmd "set hbm_inst \[ create_bd_cell -type ip -vlnv xilinx.com:ip:hbm:1.0 hbm_inst ]
set_property -dict \[ list \
CONFIG.USER_AXI_CLK_FREQ {[expr {$cnfg(hclk_f)}]} \
@ -363,7 +370,7 @@ proc cr_bd_design_hbm { parentCell } {
CONFIG.USER_CLK_SEL_LIST0 {AXI_15_ACLK} \
CONFIG.USER_CLK_SEL_LIST1 {AXI_31_ACLK} \
CONFIG.USER_DIS_REF_CLK_BUFG {TRUE} \
CONFIG.USER_HBM_DENSITY {8GB} \
CONFIG.USER_HBM_DENSITY {$hbm_density} \
CONFIG.USER_HBM_STACK {2} \
CONFIG.USER_INIT_TIMEOUT_VAL {0} \
CONFIG.USER_MC0_ECC_SCRUB_PERIOD {0x0032} \