From 572089b205b91d33ffdda172c543659d5a3f7d09 Mon Sep 17 00:00:00 2001 From: kodario Date: Mon, 14 Nov 2022 11:09:28 +0100 Subject: [PATCH] slice params. --- hw/CMakeLists.txt | 21 +++ hw/scripts/config.tcl.in | 158 +++++++++++--------- hw/scripts/wr_hdl/template_gen/lynx_pkg.txt | 38 ++--- 3 files changed, 129 insertions(+), 88 deletions(-) diff --git a/hw/CMakeLists.txt b/hw/CMakeLists.txt index 87fd05b..5efad5b 100644 --- a/hw/CMakeLists.txt +++ b/hw/CMakeLists.txt @@ -178,6 +178,27 @@ set(EN_NRU 0 CACHE STRING "Enable NRU eviction policy.") # Enable statistics set(EN_STATS 1 CACHE STRING "Enable sysfs statistics.") +# Reg stages +set(NR_DH_S0 4 CACHE STRING "Dynamic host stage 0.") +set(NR_DH_S1 3 CACHE STRING "Dynamic host stage 1.") +set(NR_DH_S2 3 CACHE STRING "Dynamic host stage 2.") +set(NR_DC_S0 4 CACHE STRING "Dynamic card stage 0.") +set(NR_DC_S1 3 CACHE STRING "Dynamic card stage 1.") +set(NR_DC_S2 3 CACHE STRING "Dynamic card stage 2.") +set(NR_DN_S0 4 CACHE STRING "Dynamic net stage 0.") +set(NR_DN_S1 3 CACHE STRING "Dynamic net stage 1.") +set(NR_DN_S2 4 CACHE STRING "Dynamic net stage 2.") +set(NR_N_S0 4 CACHE STRING "net stage 0.") +set(NR_N_S1 3 CACHE STRING "net stage 1.") +set(NR_N_S2 4 CACHE STRING "net stage 2.") +set(NR_CC 4 CACHE STRING "Static dynamic cc.") +set(NR_E_S0 3 CACHE STRING "eci stage 0.") +set(NR_E_S1 2 CACHE STRING "eci stage 1.") +set(NR_DD 4 CACHE STRING "Dynamic reg.") +set(NR_PR 4 CACHE STRING "PR reg.") +set(NR_NST 4 CACHE STRING "Net stats.") +set(NR_XST 4 CACHE STRING "XDMA stats.") + ## ## Examples ## diff --git a/hw/scripts/config.tcl.in b/hw/scripts/config.tcl.in index 90582d2..06f99c4 100644 --- a/hw/scripts/config.tcl.in +++ b/hw/scripts/config.tcl.in @@ -1,69 +1,89 @@ -set cfg(fdev) ${FDEV_NAME} -set cfg(example) ${EXAMPLE} -set cfg(shl_path) ${SHL_SCR_PATH} -set cfg(sim_path) ${SIM_SCR_PATH} -set cfg(en_hls) ${EN_HLS} -set cfg(n_reg) ${N_REGIONS} -set cfg(en_strm) ${EN_STRM} -set cfg(en_mem) ${EN_MEM} -set cfg(ddr_size) ${DDR_SIZE} -set cfg(ddr_frag) ${DDR_FRAG} -set cfg(hbm_size) ${HBM_SIZE} -set cfg(hbm_split) ${HBM_SPLIT} -set cfg(n_mem_chan) ${N_MEM_CHAN} -set cfg(n_ddr_chan) ${N_DDR_CHAN} -set cfg(n_tcp_chan) ${N_TCP_CHAN} -set cfg(en_dcard) ${EN_DCARD} -set cfg(en_hcard) ${EN_HCARD} -set cfg(en_card) ${EN_CARD} -set cfg(en_pr) ${EN_PR} -set cfg(n_config) ${N_CONFIG} -set cfg(n_outs) ${N_OUTSTANDING} -set cfg(en_bpss) ${EN_BPSS} -set cfg(en_avx) ${EN_AVX} -set cfg(en_tlbf) ${EN_TLBF} -set cfg(en_wb) ${EN_WB} -set cfg(en_rdma_0) ${EN_RDMA_0} -set cfg(en_rdma_1) ${EN_RDMA_1} -set cfg(en_tcp_0) ${EN_TCP_0} -set cfg(en_tcp_1) ${EN_TCP_1} -set cfg(pmtu) ${PMTU_BYTES} -set cfg(cores) ${COMP_CORES} -set cfg(probe) ${PROBE_ID} -set cfg(en_aclk) ${EN_ACLK} -set cfg(en_nclk) ${EN_NCLK} -set cfg(en_uclk) ${EN_UCLK} -set cfg(aclk_f) ${ACLK_F} -set cfg(nclk_f) ${NCLK_F} -set cfg(uclk_f) ${UCLK_F} -set cfg(hclk_f) ${HCLK_F} -set cfg(en_uc) ${EN_UC} -set cfg(n_chan) ${N_CHAN} -set cfg(en_rdma) ${EN_RDMA} -set cfg(en_tcp) ${EN_TCP} -set cfg(en_net_0) ${EN_NET_0} -set cfg(en_net_1) ${EN_NET_1} -set cfg(en_net) ${EN_NET} -set cfg(pol_inv) ${POL_INV} -set cfg(ddr_0) ${DDR_0} -set cfg(ddr_1) ${DDR_1} -set cfg(ddr_2) ${DDR_2} -set cfg(ddr_3) ${DDR_3} -set cfg(strm_chan) ${STRM_CHAN} -set cfg(ddr_chan) ${DDR_CHAN} -set cfg(pr_chan) ${PR_CHAN} -set cfg(uc_chan) ${UC_CHAN} -set cfg(en_xch_0) ${EN_XCH_0} -set cfg(en_xch_1) ${EN_XCH_1} -set cfg(en_xch_2) ${EN_XCH_2} -set cfg(en_xch_3) ${EN_XCH_3} -set cfg(tlbs_s) ${TLBS_S} -set cfg(tlbs_a) ${TLBS_A} -set cfg(tlbl_s) ${TLBL_S} -set cfg(tlbl_a) ${TLBL_A} -set cfg(tlbl_bits) ${TLBL_BITS} -set cfg(tlbs_bits) ${TLBS_BITS} -set cfg(en_nru) ${EN_NRU} -set cfg(en_rpc) ${EN_RPC} -set cfg(vit_hls) ${VITIS_HLS} -set cfg(en_stats) ${EN_STATS} \ No newline at end of file +set cfg(fdev) ${FDEV_NAME} +set cfg(example) ${EXAMPLE} +set cfg(shl_path) ${SHL_SCR_PATH} +set cfg(sim_path) ${SIM_SCR_PATH} +set cfg(en_hls) ${EN_HLS} +set cfg(n_reg) ${N_REGIONS} +set cfg(en_strm) ${EN_STRM} +set cfg(en_mem) ${EN_MEM} +set cfg(ddr_size) ${DDR_SIZE} +set cfg(ddr_frag) ${DDR_FRAG} +set cfg(hbm_size) ${HBM_SIZE} +set cfg(hbm_split) ${HBM_SPLIT} +set cfg(n_mem_chan) ${N_MEM_CHAN} +set cfg(n_ddr_chan) ${N_DDR_CHAN} +set cfg(n_tcp_chan) ${N_TCP_CHAN} +set cfg(en_dcard) ${EN_DCARD} +set cfg(en_hcard) ${EN_HCARD} +set cfg(en_card) ${EN_CARD} +set cfg(en_pr) ${EN_PR} +set cfg(n_config) ${N_CONFIG} +set cfg(n_outs) ${N_OUTSTANDING} +set cfg(en_bpss) ${EN_BPSS} +set cfg(en_avx) ${EN_AVX} +set cfg(en_tlbf) ${EN_TLBF} +set cfg(en_wb) ${EN_WB} +set cfg(en_rdma_0) ${EN_RDMA_0} +set cfg(en_rdma_1) ${EN_RDMA_1} +set cfg(en_tcp_0) ${EN_TCP_0} +set cfg(en_tcp_1) ${EN_TCP_1} +set cfg(pmtu) ${PMTU_BYTES} +set cfg(cores) ${COMP_CORES} +set cfg(probe) ${PROBE_ID} +set cfg(en_aclk) ${EN_ACLK} +set cfg(en_nclk) ${EN_NCLK} +set cfg(en_uclk) ${EN_UCLK} +set cfg(aclk_f) ${ACLK_F} +set cfg(nclk_f) ${NCLK_F} +set cfg(uclk_f) ${UCLK_F} +set cfg(hclk_f) ${HCLK_F} +set cfg(en_uc) ${EN_UC} +set cfg(n_chan) ${N_CHAN} +set cfg(en_rdma) ${EN_RDMA} +set cfg(en_tcp) ${EN_TCP} +set cfg(en_net_0) ${EN_NET_0} +set cfg(en_net_1) ${EN_NET_1} +set cfg(en_net) ${EN_NET} +set cfg(pol_inv) ${POL_INV} +set cfg(ddr_0) ${DDR_0} +set cfg(ddr_1) ${DDR_1} +set cfg(ddr_2) ${DDR_2} +set cfg(ddr_3) ${DDR_3} +set cfg(strm_chan) ${STRM_CHAN} +set cfg(ddr_chan) ${DDR_CHAN} +set cfg(pr_chan) ${PR_CHAN} +set cfg(uc_chan) ${UC_CHAN} +set cfg(en_xch_0) ${EN_XCH_0} +set cfg(en_xch_1) ${EN_XCH_1} +set cfg(en_xch_2) ${EN_XCH_2} +set cfg(en_xch_3) ${EN_XCH_3} +set cfg(tlbs_s) ${TLBS_S} +set cfg(tlbs_a) ${TLBS_A} +set cfg(tlbl_s) ${TLBL_S} +set cfg(tlbl_a) ${TLBL_A} +set cfg(tlbl_bits) ${TLBL_BITS} +set cfg(tlbs_bits) ${TLBS_BITS} +set cfg(en_nru) ${EN_NRU} +set cfg(en_rpc) ${EN_RPC} +set cfg(vit_hls) ${VITIS_HLS} +set cfg(en_stats) ${EN_STATS} +set cfg(nr_dh_s0) ${NR_DH_S0} +set cfg(nr_dh_s1) ${NR_DH_S1} +set cfg(nr_dh_s2) ${NR_DH_S2} +set cfg(nr_dc_s0) ${NR_DC_S0} +set cfg(nr_dc_s1) ${NR_DC_S1} +set cfg(nr_dc_s2) ${NR_DC_S2} +set cfg(nr_dn_s0) ${NR_DN_S0} +set cfg(nr_dn_s1) ${NR_DN_S1} +set cfg(nr_dn_s2) ${NR_DN_S2} +set cfg(nr_n_s0) ${NR_N_S0} +set cfg(nr_n_s1) ${NR_N_S1} +set cfg(nr_n_s2) ${NR_N_S2} +set cfg(nr_cc) ${NR_CC} +set cfg(nr_e_s0) ${NR_E_S0} +set cfg(nr_e_s1) ${NR_E_S1} +set cfg(nr_dd) ${NR_DD} +set cfg(nr_pr) ${NR_PR} +set cfg(nr_nst) ${NR_NST} +set cfg(nr_xst) ${NR_XST} + diff --git a/hw/scripts/wr_hdl/template_gen/lynx_pkg.txt b/hw/scripts/wr_hdl/template_gen/lynx_pkg.txt index 2372c04..3ecb154 100644 --- a/hw/scripts/wr_hdl/template_gen/lynx_pkg.txt +++ b/hw/scripts/wr_hdl/template_gen/lynx_pkg.txt @@ -155,25 +155,25 @@ package lynxTypes; parameter integer QUEUE_DEPTH = 8; // Slices - parameter integer N_REG_DYN_HOST_S0 = 4; - parameter integer N_REG_DYN_HOST_S1 = 3; - parameter integer N_REG_DYN_HOST_S2 = 3; - parameter integer N_REG_DYN_CARD_S0 = 4; - parameter integer N_REG_DYN_CARD_S1 = 3; - parameter integer N_REG_DYN_CARD_S2 = 3; - parameter integer N_REG_DYN_NET_S0 = 4; - parameter integer N_REG_DYN_NET_S1 = 3; - parameter integer N_REG_DYN_NET_S2 = 3; - parameter integer N_REG_NET_S0 = 4; - parameter integer N_REG_NET_S1 = 3; - parameter integer N_REG_NET_S2 = 4; - parameter integer N_REG_CLK_CNVRT = 5; - parameter integer N_REG_ECI_S0 = 3; - parameter integer N_REG_ECI_S1 = 2; - parameter integer N_REG_DYN_DCPL = 4; - parameter integer N_REG_PR = 4; - parameter integer NET_STATS_DELAY = 4; - parameter integer XDMA_STATS_DELAY = 4; + parameter integer N_REG_DYN_HOST_S0 = {{ cnfg.nr_dh_s0 }}; // 4 + parameter integer N_REG_DYN_HOST_S1 = {{ cnfg.nr_dh_s1 }}; // 3 + parameter integer N_REG_DYN_HOST_S2 = {{ cnfg.nr_dh_s2 }}; // 3 + parameter integer N_REG_DYN_CARD_S0 = {{ cnfg.nr_dc_s0 }}; // 4 + parameter integer N_REG_DYN_CARD_S1 = {{ cnfg.nr_dc_s1 }}; // 3 + parameter integer N_REG_DYN_CARD_S2 = {{ cnfg.nr_dc_s2 }}; // 3 + parameter integer N_REG_DYN_NET_S0 = {{ cnfg.nr_dn_s0 }}; // 4 + parameter integer N_REG_DYN_NET_S1 = {{ cnfg.nr_dn_s1 }}; // 3 + parameter integer N_REG_DYN_NET_S2 = {{ cnfg.nr_dn_s2 }}; // 3 + parameter integer N_REG_NET_S0 = {{ cnfg.nr_n_s0 }}; // 4 + parameter integer N_REG_NET_S1 = {{ cnfg.nr_n_s1 }}; // 3 + parameter integer N_REG_NET_S2 = {{ cnfg.nr_n_s2 }}; // 4 + parameter integer N_REG_CLK_CNVRT = {{ cnfg.nr_cc }}; // 5 + parameter integer N_REG_ECI_S0 = {{ cnfg.nr_e_s0 }}; // 3 + parameter integer N_REG_ECI_S1 = {{ cnfg.nr_e_s1 }}; // 2 + parameter integer N_REG_DYN_DCPL = {{ cnfg.nr_dd }}; // 4 + parameter integer N_REG_PR = {{ cnfg.nr_pr }}; // 4 + parameter integer NET_STATS_DELAY = {{ cnfg.nr_nst }}; // 4 + parameter integer XDMA_STATS_DELAY = {{ cnfg.nr_xst }}; // 4 // Network parameter integer ARP_LUP_REQ_BITS = 32;