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changed top naming.

This commit is contained in:
d-kor 2022-10-02 18:13:41 +02:00
parent b859e2235b
commit 55113c6390
19 changed files with 417 additions and 95 deletions
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6
hw/scripts/compile.tcl.in
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@ -108,9 +108,9 @@ exec rm -rf "$build_dir/bitstreams"
file mkdir "$build_dir/bitstreams"
# Static images
exec cp "$proj_dir/lynx.runs/impl_1/top.bit" "$build_dir/bitstreams/top.bit"
if { [file exists "$proj_dir/lynx.runs/impl_1/top.ltx"] == 1} {
exec cp "$proj_dir/lynx.runs/impl_1/top.ltx" "$build_dir/bitstreams/top.ltx"
exec cp "$proj_dir/lynx.runs/impl_1/cyt_top.bit" "$build_dir/bitstreams/cyt_top.bit"
if { [file exists "$proj_dir/lynx.runs/impl_1/cyt_top.ltx"] == 1} {
exec cp "$proj_dir/lynx.runs/impl_1/cyt_top.ltx" "$build_dir/bitstreams/cyt_top.ltx"
}
# Dynamic images

2
hw/scripts/shell.tcl.in
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@ -97,7 +97,7 @@ add_files "$proj_dir/hdl/wrappers/config_0"
add_files "$proj_dir/hdl/config_0"
# Top level
set_property "top" "top" [current_fileset]
set_property "top" "cyt_top" [current_fileset]
# Constraints
add_files -norecurse -fileset [get_filesets constrs_1] "$hw_dir/constraints/$cfg(fdev)/$cfg(fdev)_base.xdc"

4
hw/scripts/sim.tcl.in
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@ -91,9 +91,11 @@ set files [list \
[file normalize "$hw_dir/hdl/common/ram/tdp_ram_nc.sv"] \
[file normalize "$hw_dir/hdl/common/regs/axisr_reg_rtl.sv"] \
[file normalize "$hw_dir/hdl/common/regs/axil_reg_rtl.sv"] \
[file normalize "$hw_dir/hdl/common/regs/axil_reg_rd.v"] \
[file normalize "$hw_dir/hdl/common/regs/axil_reg_wr.v"] \
[file normalize "$hw_dir/hdl/common/regs/meta_reg_rtl.sv"] \
]
import_files -norecurse -fileset $obj $files
add_files -norecurse -fileset $obj $files
set_property top tb_user [current_fileset]
set_property top tb_user [get_filesets sim_1]

0
hw/scripts/wr_hdl/template_gen/top_enzian.txt → hw/scripts/wr_hdl/template_gen/cyt_top_enzian.txt
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2
hw/scripts/wr_hdl/template_gen/top_u200.txt → hw/scripts/wr_hdl/template_gen/cyt_top_u200.txt
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@ -8,7 +8,7 @@ import lynxTypes::*;
//
// Top Level - Alveo u200
//
module top (
module cyt_top (
{% if cnfg.en_net_0 %}
output wire qsfp0_resetn,
output wire qsfp0_lpmode,

2
hw/scripts/wr_hdl/template_gen/top_u250.txt → hw/scripts/wr_hdl/template_gen/cyt_top_u250.txt
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@ -8,7 +8,7 @@ import lynxTypes::*;
//
// Top Level - Alveo u250
//
module top (
module cyt_top (
{% if cnfg.en_net_0 %}
output wire qsfp0_resetn,
output wire qsfp0_lpmode,

2
hw/scripts/wr_hdl/template_gen/top_u280.txt → hw/scripts/wr_hdl/template_gen/cyt_top_u280.txt
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@ -8,7 +8,7 @@ import lynxTypes::*;
//
// Top Level - Alveo u280
//
module top (
module cyt_top (
{% if cnfg.en_net_0 %}
input wire[3:0] gt0_rxp_in,
input wire[3:0] gt0_rxn_in,

2
hw/scripts/wr_hdl/template_gen/top_u50.txt → hw/scripts/wr_hdl/template_gen/cyt_top_u50.txt
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@ -8,7 +8,7 @@ import lynxTypes::*;
//
// Top Level - Alveo u50
//
module top (
module cyt_top (
{% if cnfg.en_net_0 %}
input wire[3:0] gt0_rxp_in,
input wire[3:0] gt0_rxn_in,

2
hw/scripts/wr_hdl/template_gen/top_u55c.txt → hw/scripts/wr_hdl/template_gen/cyt_top_u55c.txt
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@ -8,7 +8,7 @@ import lynxTypes::*;
//
// Top Level - Alveo u55c
//
module top (
module cyt_top (
{% if cnfg.en_net_0 %}
input wire[3:0] gt0_rxp_in,
input wire[3:0] gt0_rxn_in,

4
hw/scripts/wr_hdl/template_gen/top_vcu118.txt → hw/scripts/wr_hdl/template_gen/cyt_top_vcu118.txt
View File

@ -8,7 +8,7 @@ import lynxTypes::*;
//
// Top Level - vcu118
//
module top (
module cyt_top (
{% if cnfg.en_net_0 %}
input wire[3:0] gt0_rxp_in,
input wire[3:0] gt0_rxn_in,
@ -55,7 +55,7 @@ module top (
output wire[0:0] c1_ddr4_ck_t,
output wire[0:0] c1_ddr4_ck_c,
output wire c1_ddr4_reset_n,
inout wire[7:0] c1_ddr4_dm_dbi_n,
inout wire[7:0] c1_ddr4_dm_dbi_n,
inout wire[63:0] c1_ddr4_dq,
inout wire[7:0] c1_ddr4_dqs_t,
inout wire[7:0] c1_ddr4_dqs_c,

24
hw/scripts/wr_hdl/template_gen/dynamic_wrapper.txt
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@ -1502,12 +1502,12 @@ module design_dynamic_wrapper #(
{% endif %}
{% if cnfg.en_rdma_0 %}
{% if cnfg.en_rpc %}
.rdma_0_sq_valid (rdma_0_sq_ul[{{ i }}].valid),
.rdma_0_sq_ready (rdma_0_sq_ul[{{ i }}].ready),
.rdma_0_sq_data (rdma_0_sq_ul[{{ i }}].data),
.rdma_0_ack_valid (rdma_0_ack_ul[{{ i }}].valid),
.rdma_0_ack_ready (rdma_0_ack_ul[{{ i }}].ready),
.rdma_0_ack_data (rdma_0_ack_ul[{{ i }}].data),
.rdma_0_sq_valid (rdma_0_sq_user_ul[{{ i }}].valid),
.rdma_0_sq_ready (rdma_0_sq_user_ul[{{ i }}].ready),
.rdma_0_sq_data (rdma_0_sq_user_ul[{{ i }}].data),
.rdma_0_ack_valid (rdma_0_ack_user_ul[{{ i }}].valid),
.rdma_0_ack_ready (rdma_0_ack_user_ul[{{ i }}].ready),
.rdma_0_ack_data (rdma_0_ack_user_ul[{{ i }}].data),
{% endif %}
.rdma_0_rd_req_valid (rdma_0_rd_req_ul[{{ i }}].valid),
.rdma_0_rd_req_ready (rdma_0_rd_req_ul[{{ i }}].ready),
@ -1530,12 +1530,12 @@ module design_dynamic_wrapper #(
{% endif %}
{% if cnfg.en_rdma_1 %}
{% if cnfg.en_rpc %}
.rdma_1_sq_valid (rdma_1_sq_ul[{{ i }}].valid),
.rdma_1_sq_ready (rdma_1_sq_ul[{{ i }}].ready),
.rdma_1_sq_data (rdma_1_sq_ul[{{ i }}].data),
.rdma_1_ack_valid (rdma_1_ack_ul[{{ i }}].valid),
.rdma_1_ack_ready (rdma_1_ack_ul[{{ i }}].ready),
.rdma_1_ack_data (rdma_1_ack_ul[{{ i }}].data),
.rdma_1_sq_valid (rdma_1_sq_user_ul[{{ i }}].valid),
.rdma_1_sq_ready (rdma_1_sq_user_ul[{{ i }}].ready),
.rdma_1_sq_data (rdma_1_sq_user_ul[{{ i }}].data),
.rdma_1_ack_valid (rdma_1_ack_user_ul[{{ i }}].valid),
.rdma_1_ack_ready (rdma_1_ack_user_ul[{{ i }}].ready),
.rdma_1_ack_data (rdma_1_ack_user_ul[{{ i }}].data),
{% endif %}
.rdma_1_rd_req_valid (rdma_1_rd_req_ul[{{ i }}].valid),
.rdma_1_rd_req_ready (rdma_1_rd_req_ul[{{ i }}].ready),

19
hw/scripts/wr_hdl/template_gen/lynx_hls.txt
View File

@ -27,6 +27,9 @@
{% if cnfg.en_tcp %}
#define EN_TCP
{% endif %}
{% if cnfg.en_rpc %}
#define EN_RPC
{% endif %}
#define AXI_DATA_BITS 512
@ -105,8 +108,8 @@ struct doneIntf {
};
{% endif %}
{% if cnfg.en_rdma %}
// RDMA interfaces
{% if cnfg.en_rpc %}
// RPC commands
struct rdmaIntf {
ap_uint<RDMA_OPCODE_BITS> opcode;
ap_uint<RDMA_QPN_BITS> qpn;
@ -122,6 +125,18 @@ struct rdmaIntf {
: opcode(opcode), qpn(qpn), host(host), mode(mode), last(last), rsrvd(0), msg(msg) {}
};
// RPC acks
struct ackIntf {
ap_uint<PID_BITS> pid;
ap_uint<DEST_BITS> vfid;
ap_uint<1> nack;
ackIntf()
: pid(0), vfid(0), nack(0) {}
rdmaIntf(ap_uint<PID_BITS> pid, ap_uint<DEST_BITS> vfid, ap_uint<1> nack)
: pid(pid), vfid(vfid), nack(nack) {}
};
{% endif %}
{% if cnfg.en_tcp %}
// TCP/IP interfaces

120
hw/scripts/wr_hdl/template_gen/user_hls.txt
View File

@ -41,28 +41,34 @@ void design_user_hls_c{{ c_cnfg }}_{{ c_reg }}_top (
hls::stream<reqIntf>& rdma_0_rd_req,
hls::stream<reqIntf>& rdma_0_wr_req,
// RDMA rq and sq
hls::stream<rdmaIntf>& rdma_0_rq,
hls::stream<rdmaIntf>& rdma_0_sq,
// RDMA streams
hls::stream<ap_axiu<AXI_DATA_BITS, 0, PID_BITS, 0> >& axis_rdma_0_sink,
hls::stream<ap_axiu<AXI_DATA_BITS, 0, PID_BITS, 0> >& axis_rdma_0_src,
{% if cnfg.en_rpc %}
// RDMA rq, sq and ack
hls::stream<rdmaIntf>& rdma_0_rq,
hls::stream<rdmaIntf>& rdma_0_sq,
hls::stream<ackIntf>& rdma_0_ack,
{% endif %}
{% endif %}
{% if cnfg.en_rdma_1 %}
// RDMA descriptors
hls::stream<reqIntf>& rdma_1_rd_req,
hls::stream<reqIntf>& rdma_1_wr_req,
// RDMA rq and sq
hls::stream<rdmaIntf>& rdma_1_rq,
hls::stream<rdmaIntf>& rdma_1_sq,
// RDMA streams
hls::stream<ap_axiu<AXI_DATA_BITS, 0, PID_BITS, 0> >& axis_rdma_1_sink,
hls::stream<ap_axiu<AXI_DATA_BITS, 0, PID_BITS, 0> >& axis_rdma_1_src,
{% if cnfg.en_rpc %}
// RDMA rq and sq
hls::stream<rdmaIntf>& rdma_1_rq,
hls::stream<rdmaIntf>& rdma_1_sq,
hls::stream<ackIntf>& rdma_1_ack,
{% endif %}
{% endif %}
{% if cnfg.en_tcp_0 %}
// TCP/IP descriptors
@ -131,26 +137,36 @@ void design_user_hls_c{{ c_cnfg }}_{{ c_reg }}_top (
#pragma HLS INTERFACE axis register port=rdma_0_wr_req name=s_rdma_0_wr_req
#pragma HLS aggregate variable=rdma_0_rd_req compact=bit
#pragma HLS aggregate variable=rdma_0_wr_req compact=bit
#pragma HLS INTERFACE axis register port=rdma_0_rq name=rdma_0_rq
#pragma HLS INTERFACE axis register port=rdma_0_sq name=rdma_0_sq
#pragma HLS aggregate variable=rdma_0_rq compact=bit
#pragma HLS aggregate variable=rdma_0_sq compact=bit
#pragma HLS INTERFACE axis register port=axis_rdma_0_sink name=s_axis_rdma_0_sink
#pragma HLS INTERFACE axis register port=axis_rdma_0_src name=m_axis_rdma_0_src
{% if cnfg.en_rpc %}
#pragma HLS INTERFACE axis register port=rdma_0_rq name=rdma_0_rq
#pragma HLS INTERFACE axis register port=rdma_0_sq name=rdma_0_sq
#pragma HLS INTERFACE axis register port=rdma_0_ack name=rdma_0_ack
#pragma HLS aggregate variable=rdma_0_rq compact=bit
#pragma HLS aggregate variable=rdma_0_sq compact=bit
#pragma HLS aggregate variable=rdma_0_ack compact=bit
{% endif %}
{% endif %}
{% if cnfg.en_rdma_1 %}
#pragma HLS INTERFACE axis register port=rdma_1_rd_req name=s_rdma_1_rd_req
#pragma HLS INTERFACE axis register port=rdma_1_wr_req name=s_rdma_1_wr_req
#pragma HLS aggregate variable=rdma_1_rd_req compact=bit
#pragma HLS aggregate variable=rdma_1_wr_req compact=bit
#pragma HLS INTERFACE axis register port=rdma_1_rq name=rdma_1_rq
#pragma HLS INTERFACE axis register port=rdma_1_sq name=rdma_1_sq
#pragma HLS aggregate variable=rdma_1_rq compact=bit
#pragma HLS aggregate variable=rdma_1_sq compact=bit
#pragma HLS INTERFACE axis register port=axis_rdma_1_sink name=s_axis_rdma_1_sink
#pragma HLS INTERFACE axis register port=axis_rdma_1_src name=m_axis_rdma_1_src
{% if cnfg.en_rpc %}
#pragma HLS INTERFACE axis register port=rdma_1_rq name=rdma_1_rq
#pragma HLS INTERFACE axis register port=rdma_1_sq name=rdma_1_sq
#pragma HLS INTERFACE axis register port=rdma_1_ack name=rdma_1_ack
#pragma HLS aggregate variable=rdma_1_rq compact=bit
#pragma HLS aggregate variable=rdma_1_sq compact=bit
#pragma HLS aggregate variable=rdma_1_ack compact=bit
{% endif %}
{% endif %}
{% if cnfg.en_tcp_0 %}
#pragma HLS INTERFACE axis register port=tcp_0_listen_req name=m_tcp_0_listen_req
@ -235,18 +251,26 @@ void design_user_hls_c{{ c_cnfg }}_{{ c_reg }}_top (
reqIntf tmp_rdma_0_wr_req = rdma_0_wr_req.read();
ap_axiu<AXI_DATA_BITS, 0, PID_BITS, 0> tmp_axis_rdma_0_sink = axis_rdma_0_sink.read();
axis_rdma_0_src.write(ap_axiu<AXI_DATA_BITS, 0, PID_BITS, 0>());
{% if cnfg.en_rpc %}
rdmaIntf tmp_rdma_0_rq = rdma_0_rq.read();
ackIntf tmp_rdma_0_ack = rdma_0_ack.read();
rdma_0_sq.write(rdmaIntf());
{% endif %}
{% endif %}
{% if cnfg.en_rdma_1 %}
reqIntf tmp_rdma_1_rd_req = rdma_1_rd_req.read();
reqIntf tmp_rdma_1_wr_req = rdma_1_wr_req.read();
ap_axiu<AXI_DATA_BITS, 0, PID_BITS, 0> tmp_axis_rdma_1_sink = axis_rdma_1_sink.read();
axis_rdma_1_src.write(ap_axiu<AXI_DATA_BITS, 0, PID_BITS, 0>());
rdmaIntf tmp_rdma_1_rq = rdma_1_rq.read();
rdma_1_sq.write(rdmaIntf());
{% if cnfg.en_rpc %}
rdmaIntf tmp_rdma_1_rq = rdma_1_rq.read();
ackIntf tmp_rdma_1_ack = rdma_1_ack.read();
rdma_1_sq.write(rdmaIntf());
{% endif %}
{% endif %}
{% if cnfg.en_tcp_0 %}
tcp_0_listen_req.write(tcpListenReqIntf());
@ -307,28 +331,34 @@ void design_user_hls_c{{ c_cnfg }}_{{ c_reg }}_top (
hls::stream<reqIntf>& rdma_0_rd_req,
hls::stream<reqIntf>& rdma_0_wr_req,
// RDMA rq and sq
hls::stream<rdmaIntf>& rdma_0_rq,
hls::stream<rdmaIntf>& rdma_0_sq,
// RDMA streams
hls::stream<axisIntf>& axis_rdma_0_sink,
hls::stream<axisIntf>& axis_rdma_0_src,
{% if cnfg.en_rpc %}
// RDMA rq, sq and ack
hls::stream<rdmaIntf>& rdma_0_rq,
hls::stream<rdmaIntf>& rdma_0_sq,
hls::stream<ackIntf>& rdma_0_ack,
{% endif %}
{% endif %}
{% if cnfg.en_rdma_1 %}
// RDMA descriptors
hls::stream<reqIntf>& rdma_1_rd_req,
hls::stream<reqIntf>& rdma_1_wr_req,
// RDMA rq and sq
hls::stream<rdmaIntf>& rdma_1_rq,
hls::stream<rdmaIntf>& rdma_1_sq,
// RDMA streams
hls::stream<axisIntf>& axis_rdma_1_sink,
hls::stream<axisIntf>& axis_rdma_1_src,
{% if cnfg.en_rpc %}
// RDMA rq and sq
hls::stream<rdmaIntf>& rdma_1_rq,
hls::stream<rdmaIntf>& rdma_1_sq,
hls::stream<ackIntf>& rdma_1_ack,
{% endif %}
{% endif %}
{% if cnfg.en_tcp_0 %}
// TCP/IP descriptors
@ -397,26 +427,36 @@ void design_user_hls_c{{ c_cnfg }}_{{ c_reg }}_top (
#pragma HLS INTERFACE axis register port=rdma_0_wr_req name=s_rdma_0_wr_req
#pragma HLS DATA_PACK variable=rdma_0_rd_req
#pragma HLS DATA_PACK variable=rdma_0_wr_req
#pragma HLS INTERFACE axis register port=rdma_0_rq name=rdma_0_rq
#pragma HLS INTERFACE axis register port=rdma_0_sq name=rdma_0_sq
#pragma HLS DATA_PACK variable=rdma_0_rq
#pragma HLS DATA_PACK variable=rdma_0_sq
#pragma HLS INTERFACE axis register port=axis_rdma_0_sink name=s_axis_rdma_0_sink
#pragma HLS INTERFACE axis register port=axis_rdma_0_src name=m_axis_rdma_0_src
{% if cnfg.en_rpc %}
#pragma HLS INTERFACE axis register port=rdma_0_rq name=rdma_0_rq
#pragma HLS INTERFACE axis register port=rdma_0_sq name=rdma_0_sq
#pragma HLS INTERFACE axis register port=rdma_0_ack name=rdma_0_ack
#pragma HLS DATA_PACK variable=rdma_0_rq
#pragma HLS DATA_PACK variable=rdma_0_sq
#pragma HLS DATA_PACK variable=rdma_0_ack
{% endif %}
{% endif %}
{% if cnfg.en_rdma_1 %}
#pragma HLS INTERFACE axis register port=rdma_1_rd_req name=s_rdma_1_rd_req
#pragma HLS INTERFACE axis register port=rdma_1_wr_req name=s_rdma_1_wr_req
#pragma HLS DATA_PACK variable=rdma_1_rd_req
#pragma HLS DATA_PACK variable=rdma_1_wr_req
#pragma HLS INTERFACE axis register port=rdma_1_rq name=rdma_1_rq
#pragma HLS INTERFACE axis register port=rdma_1_sq name=rdma_1_sq
#pragma HLS DATA_PACK variable=rdma_1_rq
#pragma HLS DATA_PACK variable=rdma_1_sq
#pragma HLS INTERFACE axis register port=axis_rdma_1_sink name=s_axis_rdma_1_sink
#pragma HLS INTERFACE axis register port=axis_rdma_1_src name=m_axis_rdma_1_src
{% if cnfg.en_rpc %}
#pragma HLS INTERFACE axis register port=rdma_1_rq name=rdma_1_rq
#pragma HLS INTERFACE axis register port=rdma_1_sq name=rdma_1_sq
#pragma HLS INTERFACE axis register port=rdma_1_ack name=rdma_1_ack
#pragma HLS DATA_PACK variable=rdma_1_rq
#pragma HLS DATA_PACK variable=rdma_1_sq
#pragma HLS DATA_PACK variable=rdma_1_ack
{% endif %}
{% endif %}
{% if cnfg.en_tcp_0 %}
#pragma HLS INTERFACE axis register port=tcp_0_listen_req name=m_tcp_0_listen_req
@ -501,18 +541,26 @@ void design_user_hls_c{{ c_cnfg }}_{{ c_reg }}_top (
reqIntf tmp_rdma_0_wr_req = rdma_0_wr_req.read();
axisIntf tmp_axis_rdma_0_sink = axis_rdma_0_sink.read();
axis_rdma_0_src.write(axisIntf());
{% if cnfg.en_rpc %}
rdmaIntf tmp_rdma_0_rq = rdma_0_rq.read();
ackIntf tmp_rdma_0_ack = rdma_0_ack.read();
rdma_0_sq.write(rdmaIntf());
{% endif %}
{% endif %}
{% if cnfg.en_rdma_1 %}
reqIntf tmp_rdma_1_rd_req = rdma_1_rd_req.read();
reqIntf tmp_rdma_1_wr_req = rdma_1_wr_req.read();
axisIntf tmp_axis_rdma_1_sink = axis_rdma_1_sink.read();
axis_rdma_1_src.write(axisIntf());
rdmaIntf tmp_rdma_1_rq = rdma_1_rq.read();
rdma_1_sq.write(rdmaIntf());
{% if cnfg.en_rpc %}
rdmaIntf tmp_rdma_1_rq = rdma_1_rq.read();
ackIntf tmp_rdma_1_ack = rdma_1_ack.read();
rdma_1_sq.write(rdmaIntf());
{% endif %}
{% endif %}
{% if cnfg.en_tcp_0 %}
tcp_0_listen_req.write(tcpListenReqIntf());

8
hw/scripts/wr_hdl/template_gen/user_logic.txt
View File

@ -46,6 +46,7 @@ module design_user_logic_c{{ c_cnfg }}_{{ c_reg }} (
// RDMA QSFP0 SQ and RQ
metaIntf.m rdma_0_sq,
metaIntf.s rdma_0_rq,
metaIntf.s rdma_0_ack,
{% endif %}
{% endif %}
@ -62,6 +63,7 @@ module design_user_logic_c{{ c_cnfg }}_{{ c_reg }} (
// RDMA QSFP1 SQ and RQ
metaIntf.m rdma_1_sq,
metaIntf.s rdma_1_rq,
metaIntf.s rdma_1_ack,
{% endif %}
{% endif %}
@ -129,7 +131,8 @@ module design_user_logic_c{{ c_cnfg }}_{{ c_reg }} (
//always_comb axis_rdma_0_src.tie_off_m();
{% if cnfg.en_rpc %}
//always_comb rdma_0_sq.tie_off_m();
//always_comb rdma_0_rq.tie_off_m();
//always_comb rdma_0_rq.tie_off_s();
//always_comb rdma_0_ack.tie_off_s();
{% endif %}
{% endif %}
{% if cnfg.en_rdma_1 %}
@ -139,7 +142,8 @@ module design_user_logic_c{{ c_cnfg }}_{{ c_reg }} (
//always_comb axis_rdma_1_src.tie_off_m();
{% if cnfg.en_rpc %}
//always_comb rdma_1_sq.tie_off_m();
//always_comb rdma_1_rq.tie_off_m();
//always_comb rdma_1_rq.tie_off_s();
//always_comb rdma_1_ack.tie_off_s();
{% endif %}
{% endif %}
{% if cnfg.en_tcp_0 %}

294
hw/scripts/wr_hdl/template_gen/user_wrapper.txt
View File

@ -97,6 +97,9 @@ module design_user_wrapper_{{ c_reg }} (
output logic rdma_0_sq_valid,
input logic rdma_0_sq_ready,
output rdma_req_t rdma_0_sq_data,
input logic rdma_0_ack_valid,
output logic rdma_0_ack_ready,
input rdma_req_t rdma_0_ack_data,
{% endif %}
// AXI4S RDMA QSFP0 SINK
@ -130,6 +133,9 @@ module design_user_wrapper_{{ c_reg }} (
output logic rdma_1_sq_valid,
input logic rdma_1_sq_ready,
output rdma_req_t rdma_1_sq_data,
input logic rdma_1_ack_valid,
output logic rdma_1_ack_ready,
input rdma_req_t rdma_1_ack_data,
{% endif %}
// AXI4S RDMA QSFP1 SINK
@ -396,6 +402,7 @@ module design_user_wrapper_{{ c_reg }} (
// RDMA rq and sq
metaIntf #(.STYPE(rdma_req_t)) rdma_0_sq();
metaIntf #(.STYPE(rdma_req_t)) rdma_0_rq();
metaIntf #(.STYPE(rdma_ack_t)) rdma_0_ack();
assign rdma_0_sq_valid = rdma_0_sq.valid;
assign rdma_0_sq.ready = rdma_0_sq_ready;
@ -411,6 +418,11 @@ module design_user_wrapper_{{ c_reg }} (
.m_axis_wr(axis_rdma_0_sink_mux),
.m_rq(rdma_0_rq)
);
assign rdma_0_ack.valid = rdma_0_ack_valid;
assign rdma_0_ack_ready = rdma_0_ack.ready;
assign rdma_0_ack.data = rdma_0_sq_data;
{% else %}
`META_ASSIGN(rdma_0_wr_req, rdma_0_wr_req_mux)
`AXISR_ASSIGN(axis_rdma_0_sink, axis_rdma_0_sink_mux)
@ -469,6 +481,11 @@ module design_user_wrapper_{{ c_reg }} (
.m_axis_wr(axis_rdma_1_sink_mux),
.m_rq(rdma_1_rq)
);
assign rdma_1_ack.valid = rdma_1_ack_valid;
assign rdma_1_ack_ready = rdma_1_ack.ready;
assign rdma_1_ack.data = rdma_1_sq_data;
{% else %}
`META_ASSIGN(rdma_1_wr_req, rdma_1_wr_req_mux)
`AXISR_ASSIGN(axis_rdma_1_sink, axis_rdma_1_sink_mux)
@ -646,6 +663,225 @@ module design_user_wrapper_{{ c_reg }} (
//
`ifdef EN_HLS
`ifdef VIT_HLS
design_user_hls_c{{ c_cnfg }}_{{ c_reg }} inst_user_c{{ c_cnfg }}_{{ c_reg }} (
.s_axi_control_AWVALID(axi_ctrl_user.awvalid),
.s_axi_control_AWREADY(axi_ctrl_user.awready),
.s_axi_control_AWADDR(axi_ctrl_user.awaddr),
.s_axi_control_WVALID(axi_ctrl_user.wvalid),
.s_axi_control_WREADY(axi_ctrl_user.wready),
.s_axi_control_WDATA(axi_ctrl_user.wdata),
.s_axi_control_WSTRB(axi_ctrl_user.wstrb),
.s_axi_control_ARVALID(axi_ctrl_user.arvalid),
.s_axi_control_ARREADY(axi_ctrl_user.arready),
.s_axi_control_ARADDR(axi_ctrl_user.araddr),
.s_axi_control_RVALID(axi_ctrl_user.rvalid),
.s_axi_control_RREADY(axi_ctrl_user.rready),
.s_axi_control_RDATA(axi_ctrl_user.rdata),
.s_axi_control_RRESP(axi_ctrl_user.rresp),
.s_axi_control_BVALID(axi_ctrl_user.bvalid),
.s_axi_control_BREADY(axi_ctrl_user.bready),
.s_axi_control_BRESP(axi_ctrl_user.bresp),
{% if cnfg.en_bpss %}
.m_bpss_rd_req_TDATA(bpss_rd_req.data),
.m_bpss_rd_req_TVALID(bpss_rd_req.valid),
.m_bpss_rd_req_TREADY(bpss_rd_req.ready),
.m_bpss_wr_req_TDATA(bpss_wr_req.data),
.m_bpss_wr_req_TVALID(bpss_wr_req.valid),
.m_bpss_wr_req_TREADY(bpss_wr_req.ready),
.s_bpss_rd_done_TDATA(bpss_rd_done.data),
.s_bpss_rd_done_TVALID(bpss_rd_done.valid),
.s_bpss_rd_done_TREADY(),
.s_bpss_wr_done_TDATA(bpss_wr_done.data),
.s_bpss_wr_done_TVALID(bpss_wr_done.valid),
.s_bpss_wr_done_TREADY(),
{% endif %}
{% if cnfg.en_strm %}
.s_axis_host_sink_TDATA(axis_host_sink.tdata),
.s_axis_host_sink_TKEEP(axis_host_sink.tkeep),
.s_axis_host_sink_TID(axis_host_sink.tid),
.s_axis_host_sink_TLAST(axis_host_sink.tlast),
.s_axis_host_sink_TVALID(axis_host_sink.tvalid),
.s_axis_host_sink_TREADY(axis_host_sink.tready),
.m_axis_host_src_TDATA(axis_host_src.tdata),
.m_axis_host_src_TKEEP(axis_host_src.tkeep),
.m_axis_host_src_TID(axis_host_src.tid),
.m_axis_host_src_TLAST(axis_host_src.tlast),
.m_axis_host_src_TVALID(axis_host_src.tvalid),
.m_axis_host_src_TREADY(axis_host_src.tready),
{% endif %}
{% if cnfg.en_mem %}
.s_axis_card_sink_TDATA(axis_card_sink.tdata),
.s_axis_card_sink_TKEEP(axis_card_sink.tkeep),
.s_axis_card_sink_TID(axis_card_sink.tid),
.s_axis_card_sink_TLAST(axis_card_sink.tlast),
.s_axis_card_sink_TVALID(axis_card_sink.tvalid),
.s_axis_card_sink_TREADY(axis_card_sink.tready),
.m_axis_card_src_TDATA(axis_card_src.tdata),
.m_axis_card_src_TKEEP(axis_card_src.tkeep),
.m_axis_card_src_TID(axis_card_src.tid),
.m_axis_card_src_TLAST(axis_card_src.tlast),
.m_axis_card_src_TVALID(axis_card_src.tvalid),
.m_axis_card_src_TREADY(axis_card_src.tready),
{% endif %}
{% if cnfg.en_rdma_0 %}
.s_rdma_0_rd_req_TDATA(rdma_0_rd_req.data),
.s_rdma_0_rd_req_TVALID(rdma_0_rd_req.valid),
.s_rdma_0_rd_req_TREADY(rdma_0_rd_req.ready),
.s_rdma_0_wr_req_TDATA(rdma_0_wr_req_mux.data),
.s_rdma_0_wr_req_TVALID(rdma_0_wr_req_mux.valid),
.s_rdma_0_wr_req_TREADY(rdma_0_wr_req_mux.ready),
.s_axis_rdma_0_sink_TDATA(axis_rdma_0_sink_mux.tdata),
.s_axis_rdma_0_sink_TKEEP(axis_rdma_0_sink_mux.tkeep),
.s_axis_rdma_0_sink_TID(axis_rdma_0_sink_mux.tid),
.s_axis_rdma_0_sink_TLAST(axis_rdma_0_sink_mux.tlast),
.s_axis_rdma_0_sink_TVALID(axis_rdma_0_sink_mux.tvalid),
.s_axis_rdma_0_sink_TREADY(axis_rdma_0_sink_mux.tready),
.m_axis_rdma_0_src_TDATA(axis_rdma_0_src.tdata),
.m_axis_rdma_0_src_TKEEP(axis_rdma_0_src.tkeep),
.m_axis_rdma_0_src_TID(axis_rdma_0_src.tid),
.m_axis_rdma_0_src_TLAST(axis_rdma_0_src.tlast),
.m_axis_rdma_0_src_TVALID(axis_rdma_0_src.tvalid),
.m_axis_rdma_0_src_TREADY(axis_rdma_0_src.tready),
{% if cnfg.en_rpc %}
.m_rdma_0_sq_TDATA(rdma_0_sq.data),
.m_rdma_0_sq_TVALID(rdma_0_sq.valid),
.m_rdma_0_sq_TREADY(rdma_0_sq.ready),
.s_rdma_0_rq_TDATA(rdma_0_rq.data),
.s_rdma_0_rq_TVALID(rdma_0_rq.valid),
.s_rdma_0_rq_TREADY(rdma_0_rq.ready),
.s_rdma_0_ack_TDATA(rdma_0_ack.data),
.s_rdma_0_ack_TVALID(rdma_0_ack.valid),
.s_rdma_0_ack_TREADY(rdma_0_ack.ready),
{% endif %}
{% endif %}
{% if cnfg.en_rdma_1 %}
.s_rdma_1_rd_req_TDATA(rdma_1_rd_req.data),
.s_rdma_1_rd_req_TVALID(rdma_1_rd_req.valid),
.s_rdma_1_rd_req_TREADY(rdma_1_rd_req.ready),
.s_rdma_1_wr_req_TDATA(rdma_1_wr_req_mux.data),
.s_rdma_1_wr_req_TVALID(rdma_1_wr_req_mux.valid),
.s_rdma_1_wr_req_TREADY(rdma_1_wr_req_mux.ready),
.s_axis_rdma_1_sink_TDATA(axis_rdma_1_sink_mux.tdata),
.s_axis_rdma_1_sink_TKEEP(axis_rdma_1_sink_mux.tkeep),
.s_axis_rdma_1_sink_TID(axis_rdma_1_sink_mux.tid),
.s_axis_rdma_1_sink_TLAST(axis_rdma_1_sink_mux.tlast),
.s_axis_rdma_1_sink_TVALID(axis_rdma_1_sink_mux.tvalid),
.s_axis_rdma_1_sink_TREADY(axis_rdma_1_sink_mux.tready),
.m_axis_rdma_1_src_TDATA(axis_rdma_1_src.tdata),
.m_axis_rdma_1_src_TKEEP(axis_rdma_1_src.tkeep),
.m_axis_rdma_1_src_TID(axis_rdma_1_src.tid),
.m_axis_rdma_1_src_TLAST(axis_rdma_1_src.tlast),
.m_axis_rdma_1_src_TVALID(axis_rdma_1_src.tvalid),
.m_axis_rdma_1_src_TREADY(axis_rdma_1_src.tready),
{% if cnfg.en_rpc %}
.m_rdma_1_sq_TDATA(rdma_1_sq.data),
.m_rdma_1_sq_TVALID(rdma_1_sq.valid),
.m_rdma_1_sq_TREADY(rdma_1_sq.ready),
.s_rdma_1_rq_TDATA(rdma_1_rq.data),
.s_rdma_1_rq_TVALID(rdma_1_rq.valid),
.s_rdma_1_rq_TREADY(rdma_1_rq.ready),
.s_rdma_1_ack_TDATA(rdma_1_ack.data),
.s_rdma_1_ack_TVALID(rdma_1_ack.valid),
.s_rdma_1_ack_TREADY(rdma_1_ack.ready),
{% endif %}
{% endif %}
{% if cnfg.en_tcp_0 %}
.m_tcp_0_listen_req_TDATA(tcp_0_listen_req.data),
.m_tcp_0_listen_req_TVALID(tcp_0_listen_req.valid),
.m_tcp_0_listen_req_TREADY(tcp_0_listen_req.ready),
.s_tcp_0_listen_rsp_TDATA(tcp_0_listen_rsp.data),
.s_tcp_0_listen_rsp_TVALID(tcp_0_listen_rsp.valid),
.s_tcp_0_listen_rsp_TREADY(tcp_0_listen_rsp.ready),
.m_tcp_0_open_req_TDATA(tcp_0_open_req.data),
.m_tcp_0_open_req_TVALID(tcp_0_open_req.valid),
.m_tcp_0_open_req_TREADY(tcp_0_open_req.ready),
.s_tcp_0_open_rsp_TDATA(tcp_0_open_rsp.data),
.s_tcp_0_open_rsp_TVALID(tcp_0_open_rsp.valid),
.s_tcp_0_open_rsp_TREADY(tcp_0_open_rsp.ready),
.m_tcp_0_close_req_TDATA(tcp_0_close_req.data),
.m_tcp_0_close_req_TVALID(tcp_0_close_req.valid),
.m_tcp_0_close_req_TREADY(tcp_0_close_req.ready),
.s_tcp_0_notify_TDATA(tcp_0_notify.data),
.s_tcp_0_notify_TVALID(tcp_0_notify.valid),
.s_tcp_0_notify_TREADY(tcp_0_notify.ready),
.m_tcp_0_rd_pkg_TDATA(tcp_0_rd_pkg.data),
.m_tcp_0_rd_pkg_TVALID(tcp_0_rd_pkg.valid),
.m_tcp_0_rd_pkg_TREADY(tcp_0_rd_pkg.ready),
.m_tcp_0_rx_meta_TDATA(tcp_0_rx_meta.data),
.m_tcp_0_rx_meta_TVALID(tcp_0_rx_meta.valid),
.m_tcp_0_rx_meta_TREADY(tcp_0_rx_meta.ready),
.m_tcp_0_tx_meta_TDATA(tcp_0_tx_meta.data),
.m_tcp_0_tx_meta_TVALID(tcp_0_tx_meta.valid),
.m_tcp_0_tx_meta_TREADY(tcp_0_tx_meta.valid),
.s_tcp_0_tx_stat_TDATA(tcp_0_tx_stat.data),
.s_tcp_0_tx_stat_TVALID(tcp_0_tx_stat.valid),
.s_tcp_0_tx_stat_TREADY(tcp_0_tx_stat.ready),
.s_axis_tcp_0_sink_TDATA(axis_tcp_0_sink.tdata),
.s_axis_tcp_0_sink_TKEEP(axis_tcp_0_sink.tkeep),
.s_axis_tcp_0_sink_TID(axis_tcp_0_sink.tid),
.s_axis_tcp_0_sink_TLAST(axis_tcp_0_sink.tlast),
.s_axis_tcp_0_sink_TVALID(axis_tcp_0_sink.tvalid),
.s_axis_tcp_0_sink_TREADY(axis_tcp_0_sink.tready),
.m_axis_tcp_0_src_TDATA(axis_tcp_0_src.tdata),
.m_axis_tcp_0_src_TKEEP(axis_tcp_0_src.tkeep),
.m_axis_tcp_0_src_TID(axis_tcp_0_src.tid),
.m_axis_tcp_0_src_TLAST(axis_tcp_0_src.tlast),
.m_axis_tcp_0_src_TVALID(axis_tcp_0_src.tvalid),
.m_axis_tcp_0_src_TREADY(axis_tcp_0_src.tready),
{% endif %}
{% if cnfg.en_tcp_1 %}
.m_tcp_1_listen_req_TDATA(tcp_1_listen_req.data),
.m_tcp_1_listen_req_TVALID(tcp_1_listen_req.valid),
.m_tcp_1_listen_req_TREADY(tcp_1_listen_req.ready),
.s_tcp_1_listen_rsp_TDATA(tcp_1_listen_rsp.data),
.s_tcp_1_listen_rsp_TVALID(tcp_1_listen_rsp.valid),
.s_tcp_1_listen_rsp_TREADY(tcp_1_listen_rsp.ready),
.m_tcp_1_open_req_TDATA(tcp_1_open_req.data),
.m_tcp_1_open_req_TVALID(tcp_1_open_req.valid),
.m_tcp_1_open_req_TREADY(tcp_1_open_req.ready),
.s_tcp_1_open_rsp_TDATA(tcp_1_open_rsp.data),
.s_tcp_1_open_rsp_TVALID(tcp_1_open_rsp.valid),
.s_tcp_1_open_rsp_TREADY(tcp_1_open_rsp.ready),
.m_tcp_1_close_req_TDATA(tcp_1_close_req.data),
.m_tcp_1_close_req_TVALID(tcp_1_close_req.valid),
.m_tcp_1_close_req_TREADY(tcp_1_close_req.ready),
.s_tcp_1_notify_TDATA(tcp_1_notify.data),
.s_tcp_1_notify_TVALID(tcp_1_notify.valid),
.s_tcp_1_notify_TREADY(tcp_1_notify.ready),
.m_tcp_1_rd_pkg_TDATA(tcp_1_rd_pkg.data),
.m_tcp_1_rd_pkg_TVALID(tcp_1_rd_pkg.valid),
.m_tcp_1_rd_pkg_TREADY(tcp_1_rd_pkg.ready),
.m_tcp_1_rx_meta_TDATA(tcp_1_rx_meta.data),
.m_tcp_1_rx_meta_TVALID(tcp_1_rx_meta.valid),
.m_tcp_1_rx_meta_TREADY(tcp_1_rx_meta.ready),
.m_tcp_1_tx_meta_TDATA(tcp_1_tx_meta.data),
.m_tcp_1_tx_meta_TVALID(tcp_1_tx_meta.valid),
.m_tcp_1_tx_meta_TREADY(tcp_1_tx_meta.valid),
.s_tcp_1_tx_stat_TDATA(tcp_1_tx_stat.data),
.s_tcp_1_tx_stat_TVALID(tcp_1_tx_stat.valid),
.s_tcp_1_tx_stat_TREADY(tcp_1_tx_stat.ready),
.s_axis_tcp_1_sink_TDATA(axis_tcp_1_sink.tdata),
.s_axis_tcp_1_sink_TKEEP(axis_tcp_1_sink.tkeep),
.s_axis_tcp_1_sink_TID(axis_tcp_1_sink.tid),
.s_axis_tcp_1_sink_TLAST(axis_tcp_1_sink.tlast),
.s_axis_tcp_1_sink_TVALID(axis_tcp_1_sink.tvalid),
.s_axis_tcp_1_sink_TREADY(axis_tcp_1_sink.tready),
.m_axis_tcp_1_src_TDATA(axis_tcp_1_src.tdata),
.m_axis_tcp_1_src_TKEEP(axis_tcp_1_src.tkeep),
.m_axis_tcp_1_src_TID(axis_tcp_1_src.tid),
.m_axis_tcp_1_src_TLAST(axis_tcp_1_src.tlast),
.m_axis_tcp_1_src_TVALID(axis_tcp_1_src.tvalid),
.m_axis_tcp_1_src_TREADY(axis_tcp_1_src.tready),
{% endif %}
.ap_clk(aclk),
.ap_rst_n(aresetn)
);
`else
design_user_hls_c{{ c_cnfg }}_{{ c_reg }} inst_user_c{{ c_cnfg }}_{{ c_reg }} (
.s_axi_control_AWVALID(axi_ctrl_user.awvalid),
.s_axi_control_AWREADY(axi_ctrl_user.awready),
@ -713,14 +949,6 @@ module design_user_wrapper_{{ c_reg }} (
.s_rdma_0_wr_req_V_TDATA(rdma_0_wr_req_mux.data),
.s_rdma_0_wr_req_V_TVALID(rdma_0_wr_req_mux.valid),
.s_rdma_0_wr_req_V_TREADY(rdma_0_wr_req_mux.ready),
{% if cnfg.en_rpc %}
.m_rdma_0_sq_V_TDATA(rdma_0_sq.data),
.m_rdma_0_sq_V_TVALID(rdma_0_sq.valid),
.m_rdma_0_sq_V_TREADY(rdma_0_sq.ready),
.m_rdma_0_rq_V_TDATA(rdma_0_rq.data),
.m_rdma_0_rq_V_TVALID(rdma_0_rq.valid),
.m_rdma_0_rq_V_TREADY(rdma_0_rq.ready),
{% endif %}
.s_axis_rdma_0_sink_TDATA(axis_rdma_0_sink_mux.tdata),
.s_axis_rdma_0_sink_TKEEP(axis_rdma_0_sink_mux.tkeep),
.s_axis_rdma_0_sink_TID(axis_rdma_0_sink_mux.tid),
@ -733,6 +961,17 @@ module design_user_wrapper_{{ c_reg }} (
.m_axis_rdma_0_src_TLAST(axis_rdma_0_src.tlast),
.m_axis_rdma_0_src_TVALID(axis_rdma_0_src.tvalid),
.m_axis_rdma_0_src_TREADY(axis_rdma_0_src.tready),
{% if cnfg.en_rpc %}
.m_rdma_0_sq_V_TDATA(rdma_0_sq.data),
.m_rdma_0_sq_V_TVALID(rdma_0_sq.valid),
.m_rdma_0_sq_V_TREADY(rdma_0_sq.ready),
.s_rdma_0_rq_V_TDATA(rdma_0_rq.data),
.s_rdma_0_rq_V_TVALID(rdma_0_rq.valid),
.s_rdma_0_rq_V_TREADY(rdma_0_rq.ready),
.s_rdma_0_ack_V_TDATA(rdma_0_ack.data),
.s_rdma_0_ack_V_TVALID(rdma_0_ack.valid),
.s_rdma_0_ack_V_TREADY(rdma_0_ack.ready),
{% endif %}
{% endif %}
{% if cnfg.en_rdma_1 %}
.s_rdma_1_rd_req_V_TDATA(rdma_1_rd_req.data),
@ -741,14 +980,6 @@ module design_user_wrapper_{{ c_reg }} (
.s_rdma_1_wr_req_V_TDATA(rdma_1_wr_req_mux.data),
.s_rdma_1_wr_req_V_TVALID(rdma_1_wr_req_mux.valid),
.s_rdma_1_wr_req_V_TREADY(rdma_1_wr_req_mux.ready),
{% if cnfg.en_rpc %}
.m_rdma_1_sq_V_TDATA(rdma_1_sq.data),
.m_rdma_1_sq_V_TVALID(rdma_1_sq.valid),
.m_rdma_1_sq_V_TREADY(rdma_1_sq.ready),
.m_rdma_1_rq_V_TDATA(rdma_1_rq.data),
.m_rdma_1_rq_V_TVALID(rdma_1_rq.valid),
.m_rdma_1_rq_V_TREADY(rdma_1_rq.ready),
{% endif %}
.s_axis_rdma_1_sink_TDATA(axis_rdma_1_sink_mux.tdata),
.s_axis_rdma_1_sink_TKEEP(axis_rdma_1_sink_mux.tkeep),
.s_axis_rdma_1_sink_TID(axis_rdma_1_sink_mux.tid),
@ -761,6 +992,17 @@ module design_user_wrapper_{{ c_reg }} (
.m_axis_rdma_1_src_TLAST(axis_rdma_1_src.tlast),
.m_axis_rdma_1_src_TVALID(axis_rdma_1_src.tvalid),
.m_axis_rdma_1_src_TREADY(axis_rdma_1_src.tready),
{% if cnfg.en_rpc %}
.m_rdma_1_sq_V_TDATA(rdma_1_sq.data),
.m_rdma_1_sq_V_TVALID(rdma_1_sq.valid),
.m_rdma_1_sq_V_TREADY(rdma_1_sq.ready),
.s_rdma_1_rq_V_TDATA(rdma_1_rq.data),
.s_rdma_1_rq_V_TVALID(rdma_1_rq.valid),
.s_rdma_1_rq_V_TREADY(rdma_1_rq.ready),
.s_rdma_1_ack_V_TDATA(rdma_1_ack.data),
.s_rdma_1_ack_V_TVALID(rdma_1_ack.valid),
.s_rdma_1_ack_V_TREADY(rdma_1_ack.ready),
{% endif %}
{% endif %}
{% if cnfg.en_tcp_0 %}
.m_tcp_0_listen_req_V_V_TDATA(tcp_0_listen_req.data),
@ -854,6 +1096,8 @@ module design_user_wrapper_{{ c_reg }} (
.ap_rst_n(aresetn)
);
`endif
`else
design_user_logic_c{{ c_cnfg }}_{{ c_reg }} inst_user_c{{ c_cnfg }}_{{ c_reg }} (
.axi_ctrl(axi_ctrl_user),
@ -874,22 +1118,24 @@ module design_user_wrapper_{{ c_reg }} (
{% if cnfg.en_rdma_0 %}
.rdma_0_rd_req(rdma_0_rd_req),
.rdma_0_wr_req(rdma_0_wr_req_mux),
{% if cnfg.en_rpc %}
.rdma_0_sq(rdma_0_sq),
.rdma_0_rq(rdma_0_rq),
{% endif %}
.axis_rdma_0_src(axis_rdma_0_src),
.axis_rdma_0_sink(axis_rdma_0_sink_mux),
{% if cnfg.en_rpc %}
.rdma_0_sq(rdma_0_sq),
.rdma_0_rq(rdma_0_rq),
.rdma_0_ack(rdma_0_ack),
{% endif %}
{% endif %}
{% if cnfg.en_rdma_1 %}
.rdma_1_rd_req(rdma_1_rd_req),
.rdma_1_wr_req(rdma_1_wr_req_mux),
{% if cnfg.en_rpc %}
.rdma_1_sq(rdma_1_sq),
.rdma_1_rq(rdma_1_rq),
{% endif %}
.axis_rdma_1_src(axis_rdma_1_src),
.axis_rdma_1_sink(axis_rdma_1_sink_mux),
{% if cnfg.en_rpc %}
.rdma_1_sq(rdma_1_sq),
.rdma_1_rq(rdma_1_rq),
.rdma_1_ack(rdma_1_ack),
{% endif %}
{% endif %}
{% if cnfg.en_tcp_0 %}
.tcp_0_listen_req(tcp_0_listen_req),

2
hw/scripts/wr_hdl/write_hdl.py.in
View File

@ -91,7 +91,7 @@ else :
renderwrap('lynx_pkg', 0, 0)
# Top level
renderwrap('top_' + cfg['fdev'], 0, 0)
renderwrap('cyt_top_' + cfg['fdev'], 0, 0)
# Top level shell
renderwrap('top_shell', 1, 0)

1
hw/sim/tb_templates/c_scb.svh
View File

@ -23,6 +23,7 @@ class c_scb;
function new(mailbox mon2scb, mailbox drv2scb, input c_struct_t params);
this.mon2scb = mon2scb;
this.drv2scb = drv2scb;
this.params = params;
endfunction
//

4
hw/sim/tb_templates/c_struct.sv
View File

@ -2,8 +2,8 @@ package simTypes;
// SIM
parameter CLK_PERIOD = 10ns;
parameter RST_PERIOD = 2.5 * CLK_PERIOD;
parameter AST_PERIOD = 4.5 * CLK_PERIOD;
parameter RST_PERIOD = 3 * CLK_PERIOD;
parameter AST_PERIOD = 10 * CLK_PERIOD;
parameter TT = 2ns;
parameter TA = 1ns;

14
hw/sim/tb_templates/tb_user.sv
View File

@ -6,21 +6,27 @@ import simTypes::*;
`include "c_axil.svh"
`include "c_meta.svh"
task delay(input integer n_clk_prds);
#(n_clk_prds*CLK_PERIOD);
endtask
module tb_user;
c_struct_t params;
assign params.rs_k = 3;
assign params.rs_m = 2;
assign params.n_trs = 16;
logic aclk = 1'b0;
logic aresetn = 1'b1;
logic aclk = 1'b1;
logic aresetn = 1'b0;
//clock generation
always #(CLK_PERIOD/2) aclk = ~aclk;
//reset Generation
initial begin
aresetn = 0;
#(RST_PERIOD) aresetn = 1;
aresetn = 1'b0;
#(RST_PERIOD) aresetn = 1'b1;
end
// Interfaces and drivers