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mem ip_inst fix.

This commit is contained in:
kodario 2022-10-13 14:00:34 +02:00
parent 816ed3aeda
commit 483002d953
5 changed files with 18 additions and 41 deletions
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4
hw/hdl/stripe/axi_stripe_b.sv
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@ -29,7 +29,7 @@
import lynxTypes::*;
module axi_stripe_r (
module axi_stripe_b (
input logic aclk,
input logic aresetn,
@ -133,7 +133,7 @@ for(genvar i = 0; i < N_DDR_CHAN; i++) begin
assign s_axi_bready = bready_sink[s_axi_bid];
axis_data_fifo_512_stripe_b inst_reorder (
axis_data_fifo_stripe_b inst_reorder (
.s_axis_aresetn(aresetn),
.s_axis_aclk(aclk),
.s_axis_tvalid(bvalid_sink[i]),

2
hw/hdl/stripe/axi_stripe_r.sv
View File

@ -152,7 +152,7 @@ for(genvar i = 0; i < N_DDR_CHAN; i++) begin
assign s_axi_rready = rready_sink[s_axi_rid];
axis_data_fifo_512_stripe_r inst_reorder (
axis_data_fifo_stripe_r inst_reorder (
.s_axis_aresetn(aresetn),
.s_axis_aclk(aclk),
.s_axis_tvalid(rvalid_sink[i]),

27
hw/scripts/bd/cr_hbm.tcl
View File

@ -532,27 +532,16 @@ proc cr_bd_design_hbm { parentCell } {
connect_bd_net [get_bd_pins hbm_reset_sync_SLR0/interconnect_aresetn] [get_bd_pins path_$i/hresetn]
}
if {$cnfg(vit_hls) eq 1} {
for {set i 0} {$i < $cnfg(n_mem_chan)} {incr i} {
set cmd "[format "connect_bd_intf_net \[get_bd_intf_pins hbm_inst/SAXI_%02d_8HI] -boundary_type upper \[get_bd_intf_pins path_$i/M_AXI]" $i]"
eval $cmd
}
for {set i $cnfg(n_mem_chan)} {$i < 32} {incr i} {
set cmd "[format "connect_bd_intf_net \[get_bd_intf_pins hbm_inst/SAXI_%02d_8HI] -boundary_type upper \[get_bd_intf_ports axi_toff_in_%d]" $i [expr {$i - $cnfg(n_mem_chan)}]]"
eval $cmd
}
} else {
for {set i 0} {$i < $cnfg(n_mem_chan)} {incr i} {
set cmd "[format "connect_bd_intf_net \[get_bd_intf_pins hbm_inst/SAXI_%02d] -boundary_type upper \[get_bd_intf_pins path_$i/M_AXI]" $i]"
eval $cmd
}
for {set i 0} {$i < $cnfg(n_mem_chan)} {incr i} {
set cmd "[format "connect_bd_intf_net \[get_bd_intf_pins hbm_inst/SAXI_%02d] -boundary_type upper \[get_bd_intf_pins path_$i/M_AXI]" $i]"
eval $cmd
}
for {set i $cnfg(n_mem_chan)} {$i < 32} {incr i} {
set cmd "[format "connect_bd_intf_net \[get_bd_intf_pins hbm_inst/SAXI_%02d] -boundary_type upper \[get_bd_intf_ports axi_toff_in_%d]" $i [expr {$i - $cnfg(n_mem_chan)}]]"
eval $cmd
}
}
for {set i $cnfg(n_mem_chan)} {$i < 32} {incr i} {
set cmd "[format "connect_bd_intf_net \[get_bd_intf_pins hbm_inst/SAXI_%02d] -boundary_type upper \[get_bd_intf_ports axi_toff_in_%d]" $i [expr {$i - $cnfg(n_mem_chan)}]]"
eval $cmd
}
for {set i 0} {$i < $cnfg(n_mem_chan)} {incr i} {
connect_bd_intf_net -boundary_type upper [get_bd_intf_pins path_$i/S_AXI] [get_bd_intf_ports axi_hbm_in_$i]

19
hw/scripts/bd/cr_hbm_split.tcl
View File

@ -523,7 +523,6 @@ for {set i 0} {$i < $cnfg(n_mem_chan)} {incr i} {
connect_bd_net [get_bd_ports hresetn] [get_bd_pins path_$i/hresetn]
}
if {$cnfg(vit_hls) eq 1} {
for {set i 0} {$i < $cnfg(n_mem_chan)} {incr i} {
set cmd "[format "connect_bd_intf_net \[get_bd_intf_pins hbm_inst/SAXI_%02d_8HI] -boundary_type upper \[get_bd_intf_pins path_$i/M_AXI]" $i]"
eval $cmd
@ -540,24 +539,6 @@ for {set i 0} {$i < $cnfg(n_mem_chan)} {incr i} {
set cmd "[format "connect_bd_intf_net \[get_bd_intf_pins hbm_inst/SAXI_%02d_8HI] -boundary_type upper \[get_bd_intf_ports axi_toff_in_%d]" [expr {$i + 16}] [expr {($i - $cnfg(n_mem_chan)) + (16 - $cnfg(n_mem_chan))}]]"
eval $cmd
}
} else {
for {set i 0} {$i < $cnfg(n_mem_chan)} {incr i} {
set cmd "[format "connect_bd_intf_net \[get_bd_intf_pins hbm_inst/SAXI_%02d] -boundary_type upper \[get_bd_intf_pins path_$i/M_AXI]" $i]"
eval $cmd
}
for {set i 0} {$i < $cnfg(n_mem_chan)} {incr i} {
set cmd "[format "connect_bd_intf_net \[get_bd_intf_pins hbm_inst/SAXI_%02d] -boundary_type upper \[get_bd_intf_pins path_%d/M_AXI]" [expr {$i + 16}] [expr {$i + $cnfg(n_mem_chan)}]]"
eval $cmd
}
for {set i $cnfg(n_mem_chan)} {$i < 16} {incr i} {
set cmd "[format "connect_bd_intf_net \[get_bd_intf_pins hbm_inst/SAXI_%02d] -boundary_type upper \[get_bd_intf_ports axi_toff_in_%d]" $i [expr {$i - $cnfg(n_mem_chan)}]]"
eval $cmd
set cmd "[format "connect_bd_intf_net \[get_bd_intf_pins hbm_inst/SAXI_%02d] -boundary_type upper \[get_bd_intf_ports axi_toff_in_%d]" [expr {$i + 16}] [expr {($i - $cnfg(n_mem_chan)) + (16 - $cnfg(n_mem_chan))}]]"
eval $cmd
}
}
for {set i 0} {$i < $cnfg(n_mem_chan)} {incr i} {

7
hw/scripts/ip_inst/base_infrastructure.tcl
View File

@ -58,6 +58,13 @@ eval $cmd
create_ip -name axis_clock_converter -vendor xilinx.com -library ip -version 1.1 -module_name axisr_clock_converter_512
set_property -dict [list CONFIG.TDATA_NUM_BYTES {64} CONFIG.HAS_TKEEP {1} CONFIG.HAS_TLAST {1} CONFIG.TID_WIDTH {6}] [get_ips axisr_clock_converter_512]
# Stripe
create_ip -name axis_data_fifo -vendor xilinx.com -library ip -version 2.0 -module_name axis_data_fifo_stripe_b
set_property -dict [list CONFIG.TDATA_NUM_BYTES {0} CONFIG.TUSER_WIDTH {2} CONFIG.Component_Name {axis_data_fifo_stripe_b}] [get_ips axis_data_fifo_stripe_b]
create_ip -name axis_data_fifo -vendor xilinx.com -library ip -version 2.0 -module_name axis_data_fifo_stripe_r
set_property -dict [list CONFIG.TDATA_NUM_BYTES {64} CONFIG.TUSER_WIDTH {2} CONFIG.HAS_TLAST {1} CONFIG.Component_Name {axis_data_fifo_stripe_r}] [get_ips axis_data_fifo_stripe_r]
# TLB
create_ip -name axis_data_fifo -vendor xilinx.com -library ip -version 2.0 -module_name axis_data_fifo_128_tlb
set_property -dict [list CONFIG.TDATA_NUM_BYTES {16} CONFIG.FIFO_DEPTH {64} CONFIG.HAS_TLAST {1} ] [get_ips axis_data_fifo_128_tlb]