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u280 timing update.

This commit is contained in:
d-kor 2022-05-17 16:11:52 +02:00
parent 6e8a1492b0
commit 334b4ce9d7
10 changed files with 31 additions and 23 deletions
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1
.gitignore vendored
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@ -6,7 +6,6 @@ hd_visual/
ip_dir/
xsim.dir/
tb_user/
ip/
.Xil/
.vscode/
*.pb

13
hw/hdl/network/cmac/cmac_uplus_axis_wrapper.sv
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@ -48,8 +48,8 @@ module cmac_axis_wrapper #(
AXI4S.s s_tx_axis,
output logic usr_clk,
output logic tx_rst,
output logic rx_rst
output logic tx_rst
//output logic rx_rst
);
// gt_rxrecclkout
@ -68,8 +68,8 @@ logic gt_rxusrclk2;
assign usr_clk = gt_txusrclk2;
// Resets
reg usr_rx_reset_r;
reg usr_rx_reset_rr;
//reg usr_rx_reset_r;
//reg usr_rx_reset_rr;
reg core_tx_reset_r;
reg core_tx_reset_rr;
@ -80,17 +80,18 @@ wire core_tx_reset_w;
assign rx_aligned = stat_rx_aligned;
// Slicing
/*
always @( posedge gt_rxusrclk2 ) begin
usr_rx_reset_r <= usr_rx_reset_w;
usr_rx_reset_rr <= usr_rx_reset_r;
end
*/
always @( posedge gt_txusrclk2 ) begin
core_tx_reset_r <= core_tx_reset_w;
core_tx_reset_rr <= core_tx_reset_r;
end
assign rx_rst = usr_rx_reset_rr;
//assign rx_rst = usr_rx_reset_rr;
assign tx_rst = core_tx_reset_rr;
//RX FSM states ----------------------------------------------------------------------

26
hw/hdl/network/cmac/network_module.sv
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@ -29,7 +29,8 @@
import lynxTypes::*;
module network_module #(
parameter integer QSFP = 0
parameter integer QSFP = 0,
parameter integer N_STGS = 2
) (
input wire init_clk,
input wire sys_reset,
@ -50,14 +51,15 @@ module network_module #(
);
wire network_init_done;
wire user_rx_reset;
//wire user_rx_reset;
wire user_tx_reset;
reg core_reset_tmp = 1'b0;
reg core_reset = 1'b0;
// Network reset
always @(posedge rclk) begin
core_reset_tmp <= !(user_tx_reset | user_rx_reset);
//core_reset_tmp <= !(user_tx_reset | user_rx_reset);
core_reset_tmp <= !(user_tx_reset);
core_reset <= core_reset_tmp;
end
assign network_init_done = core_reset;
@ -70,15 +72,21 @@ BUFG bufg_aresetn(
/*
* RX
*/
AXI4S #(.AXI4S_DATA_BITS(AXI_NET_BITS)) rx_axis_cmac();
AXI4S #(.AXI4S_DATA_BITS(AXI_NET_BITS)) rx_axis();
/*
* TX
*/
AXI4S #(.AXI4S_DATA_BITS(AXI_NET_BITS)) tx_axis_cmac();
AXI4S #(.AXI4S_DATA_BITS(AXI_NET_BITS)) tx_axis();
AXI4S #(.AXI4S_DATA_BITS(AXI_NET_BITS)) axis_tx_pkg_to_fifo();
AXI4S #(.AXI4S_DATA_BITS(AXI_NET_BITS)) axis_tx_padding_to_fifo();
// Slices
axis_reg_array #(.DATA_BITS(AXI_NET_BITS), .N_STAGES(N_STGS)) inst_rx (.aclk(rclk), .aresetn(rresetn), .s_axis(rx_axis_cmac), .m_axis(rx_axis));
axis_reg_array #(.DATA_BITS(AXI_NET_BITS), .N_STAGES(N_STGS)) inst_tx (.aclk(rclk), .aresetn(rresetn), .s_axis(tx_axis), .m_axis(tx_axis_cmac));
cmac_axis_wrapper #(
.QSFP(QSFP)
) cmac_wrapper_inst (
@ -92,12 +100,12 @@ cmac_axis_wrapper #(
.gt_txp_out(gt_txp_out),
.gt_txn_out(gt_txn_out),
.m_rx_axis(rx_axis),
.s_tx_axis(tx_axis),
.m_rx_axis(rx_axis_cmac),
.s_tx_axis(tx_axis_cmac),
.usr_clk(rclk),
.tx_rst(user_tx_reset),
.rx_rst(user_rx_reset)
.tx_rst(user_tx_reset)
//.rx_rst(user_rx_reset)
);
@ -110,7 +118,7 @@ axis_data_fifo_512_cc rx_crossing (
.s_axis_tdata(rx_axis.tdata),
.s_axis_tkeep(rx_axis.tkeep),
.s_axis_tlast(rx_axis.tlast),
.m_axis_aclk(rclk),
//.m_axis_aclk(rclk),
.m_axis_tvalid(m_axis_net_rx.tvalid),
.m_axis_tready(m_axis_net_rx.tready),
.m_axis_tdata(m_axis_net_rx.tdata),
@ -129,7 +137,7 @@ axis_data_fifo_512_cc tx_crossing (
.s_axis_tdata(axis_tx_pkg_to_fifo.tdata),
.s_axis_tkeep(axis_tx_pkg_to_fifo.tkeep),
.s_axis_tlast(axis_tx_pkg_to_fifo.tlast),
.m_axis_aclk(rclk),
//.m_axis_aclk(rclk),
.m_axis_tvalid(tx_axis.tvalid),
.m_axis_tready(tx_axis.tready),
.m_axis_tdata(tx_axis.tdata),

2
hw/hdl/network/stack/network_ccross_early.sv
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@ -39,7 +39,7 @@ import lynxTypes::*;
*/
module network_ccross_early #(
parameter integer ENABLED = 1,
parameter integer N_STGS = 3
parameter integer N_STGS = 5
) (
input wire rclk,
input wire rresetn,

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hw/ip/SmartCamCtl.dcp Normal file
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hw/ip/SmartCamCtlArp.dcp Normal file
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hw/ip/mig_7series_0.dcp Executable file
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hw/ip/mig_axi_mm_dual.dcp Normal file
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2
hw/scripts/ip_inst/network_stack.tcl
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@ -79,7 +79,7 @@ if {$cfg(fdev) eq "enzian"} {
## FIFOs
create_ip -name axis_data_fifo -vendor xilinx.com -library ip -version 2.0 -module_name axis_data_fifo_512_cc
set_property -dict [list CONFIG.TDATA_NUM_BYTES {64} CONFIG.IS_ACLK_ASYNC {1} CONFIG.HAS_TKEEP {1} CONFIG.HAS_TLAST {1} ] [get_ips axis_data_fifo_512_cc]
set_property -dict [list CONFIG.TDATA_NUM_BYTES {64} CONFIG.IS_ACLK_ASYNC {0} CONFIG.HAS_TKEEP {1} CONFIG.HAS_TLAST {1} ] [get_ips axis_data_fifo_512_cc]
create_ip -name axis_data_fifo -vendor xilinx.com -library ip -version 2.0 -module_name axis_pkg_fifo_512
set_property -dict [list CONFIG.TDATA_NUM_BYTES {64} CONFIG.FIFO_MODE {2} CONFIG.HAS_TKEEP {1} CONFIG.HAS_TLAST {1} ] [get_ips axis_pkg_fifo_512]

10
hw/scripts/wr_hdl/templates/lynx_pkg.txt
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@ -140,17 +140,17 @@ package lynxTypes;
parameter integer QUEUE_DEPTH = 8;
// Slices
parameter integer N_REG_DYN_HOST_S0 = 2;
parameter integer N_REG_DYN_HOST_S0 = 3;
parameter integer N_REG_DYN_HOST_S1 = 2;
parameter integer N_REG_DYN_HOST_S2 = 2;
parameter integer N_REG_DYN_CARD_S0 = 2;
parameter integer N_REG_DYN_CARD_S0 = 3;
parameter integer N_REG_DYN_CARD_S1 = 2;
parameter integer N_REG_DYN_CARD_S2 = 2;
parameter integer N_REG_DYN_NET_S0 = 2;
parameter integer N_REG_DYN_NET_S0 = 3;
parameter integer N_REG_DYN_NET_S1 = 2;
parameter integer N_REG_DYN_NET_S2 = 2;
parameter integer N_REG_NET_S0 = 2;
parameter integer N_REG_CLK_CNVRT = 2;
parameter integer N_REG_NET_S0 = 4;
parameter integer N_REG_CLK_CNVRT = 5;
parameter integer N_REG_ECI_S0 = 2;
parameter integer N_REG_ECI_S1 = 2;
parameter integer N_REG_DYN_DCPL = 2;