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clocks hbm.

This commit is contained in:
kodario 2022-07-11 16:18:20 +02:00
parent f69ca381e5
commit 1ff9352c19
3 changed files with 11 additions and 7 deletions
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2
hw/constraints/u50/u50_base.xdc
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@ -27,6 +27,8 @@ set_property PACKAGE_PIN BB18 [get_ports hbm_clk_clk_p] ;# Bank 64 VC
set_property IOSTANDARD LVDS [get_ports hbm_clk_clk_p] ;# Bank 64 VCCO - VCC1V8 - IO_L11P_T1U_N8_GC_64
set_property DQS_BIAS TRUE [get_ports hbm_clk_clk_p] ;# Bank 64 VCCO - VCC1V8 - IO_L11P_T1U_N8_GC_64
create_clock -period 10.000 -name hbmrefclk [get_ports hbm_clk_clk_p] ;
# Burn
set_property PACKAGE_PIN J18 [get_ports fpga_burn] ;# Bank 68 VCCO - VCC1V8 - IO_L6N_T0U_N11_AD6N_68
set_property IOSTANDARD LVCMOS18 [get_ports fpga_burn] ;# Bank 68 VCCO - VCC1V8 - IO_L6N_T0U_N11_AD6N_68

10
hw/constraints/u55c/u55c_base.xdc
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@ -23,10 +23,12 @@ set_property IOSTANDARD LVDS [get_ports user_clk_clk_p] ;# Bank 72 VCCO - V
#set_property IOSTANDARD LVDS [get_ports sysclk3_n] ;# Bank 65 VCCO - VCC1V8 - IO_L11N_T1U_N9_GC_A11_D27_65
#set_property PACKAGE_PIN BK43 [get_ports sysclk3_p] ;# Bank 65 VCCO - VCC1V8 - IO_L11P_T1U_N8_GC_A10_D26_65
#set_property IOSTANDARD LVDS [get_ports sysclk3_p] ;# Bank 65 VCCO - VCC1V8 - IO_L11P_T1U_N8_GC_A10_D26_65
set_property PACKAGE_PIN BL10 [get_ports hbm_clk_n] ;# Bank 68 VCCO - VCC1V8 - IO_L11N_T1U_N9_GC_68
set_property IOSTANDARD LVDS [get_ports hbm_clk_n] ;# Bank 68 VCCO - VCC1V8 - IO_L11N_T1U_N9_GC_68
set_property PACKAGE_PIN BK10 [get_ports hbm_clk_p] ;# Bank 68 VCCO - VCC1V8 - IO_L11P_T1U_N8_GC_68
set_property IOSTANDARD LVDS [get_ports hbm_clk_p] ;# Bank 68 VCCO - VCC1V8 - IO_L11P_T1U_N8_GC_68
set_property PACKAGE_PIN BL10 [get_ports hbm_clk_clk_n] ;# Bank 68 VCCO - VCC1V8 - IO_L11N_T1U_N9_GC_68
set_property IOSTANDARD LVDS [get_ports hbm_clk_clk_n] ;# Bank 68 VCCO - VCC1V8 - IO_L11N_T1U_N9_GC_68
set_property PACKAGE_PIN BK10 [get_ports hbm_clk_clk_p] ;# Bank 68 VCCO - VCC1V8 - IO_L11P_T1U_N8_GC_68
set_property IOSTANDARD LVDS [get_ports hbm_clk_clk_p] ;# Bank 68 VCCO - VCC1V8 - IO_L11P_T1U_N8_GC_68
create_clock -period 10.000 -name hbmrefclk [get_ports hbm_clk_clk_p] ;
# Burn
set_property PACKAGE_PIN BE45 [get_ports fpga_burn] ;# Bank 68 VCCO - VCC1V8 - IO_L6N_T0U_N11_AD6N_68

6
hw/services/network/hls/ib_transport_protocol/ib_transport_protocol.cpp
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@ -2145,8 +2145,8 @@ void ib_transport_protocol(
static stream<ackEvent> rx_ibhEventFifo("rx_ibhEventFifo"); //TODO rename
static stream<ackEvent> rx_exhEventMetaFifo("rx_exhEventMetaFifo");
static stream<memCmdInternal> rx_remoteMemCmd("rx_remoteMemCmd");
#pragma HLS STREAM depth=64 variable=rx_ibhEventFifo
#pragma HLS STREAM depth=64 variable=rx_exhEventMetaFifo
#pragma HLS STREAM depth=32 variable=rx_ibhEventFifo
#pragma HLS STREAM depth=32 variable=rx_exhEventMetaFifo
#pragma HLS STREAM depth=512 variable=rx_remoteMemCmd
#if defined( __VITIS_HLS__)
#pragma HLS aggregate variable=rx_ibhEventFifo compact=bit
@ -2289,7 +2289,7 @@ void ib_transport_protocol(
#pragma HLS STREAM depth=4 variable=exh_lengthFifo
#pragma HLS STREAM depth=8 variable=rx_readRequestFifo
#pragma HLS STREAM depth=512 variable=rx_readEvenFifo
#pragma HLS STREAM depth=64 variable=rx_ackEventFifo
#pragma HLS STREAM depth=32 variable=rx_ackEventFifo
#if defined( __VITIS_HLS__)
#pragma HLS aggregate variable=rx_readRequestFifo compact=bit
#pragma HLS aggregate variable=rx_readEvenFifo compact=bit