Framework providing operating system abstractions and a range of shared networking (*RDMA*, *TCP/IP*) and memory services to common modern heterogeneuous platforms.
`Vivado` is needed to build the hardware side of things. For any HLS cores present the corresponding HLS tool also needs to be installed (`Vivado HLS` or `Vitis HLS`, depending on the version). Hardware server will be enough for deployment only scenarios. Coyote is currently being tested with `Vivado 2021.2`. Previous versions should be usable as well and should not give too many headaches.
Following Xilinx platforms are supported: `vcu118`, `Alveo u50`, `Alveo u55c`, `Alveo u200`, `Alveo u250` and `Alveo u280`. Coyote is currently being developed on the XACC cluster at ETH Zurich. For more information and possible external access check out the following link: https://xilinx.github.io/xacc/ethz.html
`CMake` is used for project creation. Additionally `Jinja2` template engine for Python is used for some of the code generation. The API is writen in `C++`, 17 should suffice (for now).
The project is created once the above command completes. Arbitrary user logic can then be inserted. If any of the existing examples are chosen, nothing needs to be done at this step.
User logic wrappers can be found under build project directory in the **hdl/config_X** where **X** represents the chosen PR configuration. Both HLS and HDL wrappers are placed in the same directories.
If multiple PR configurations are present it is advisable to put the most complex configuration in the initial one (**config_0**). Additional configurations can always be created with `make dynamic`. Explicit floorplanning should be done manually after synthesis (providing default floorplanning generally makes little sense).
Project can always be managed from Vivado GUI, for those more experienced with FPGA design flows.
Once the compilation finishes the initial bitstream with the static region can be loaded to the FPGA via JTAG. All compiled bitstreams, including partial ones, can be found in the build directory under **bitstreams**.
The API of the Coyote is present in the sw directory. Coyote is built around three software layers, each adding higher level of abstractions and parallelisation potential:
1.**cProc** - Coyote process, targets a single *vFPGA*. Multiple *cProc* objects can run within a single *vFPGA*.
2.**cThread** - Coyote thread, running on top of *cProc*. Allows the exploration of task level parallelisation.
3.**cTask** - Coyote task, arbitrary user variadic function with arbitrary parameters executed by *cThreads*.
Example projects and more info on each of these can be found under `sw/examples`.