forked from opendacs/PyHCL
395 lines
17 KiB
Python
395 lines
17 KiB
Python
# Copyright (c) 2019 scutdig
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# Licensed under the MIT license.
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from typing import List
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from pyhcl.ir.low_ir import *
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from pyhcl.ir.low_prim import *
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from pyhcl.passes._pass import Pass, PassException, Error
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from pyhcl.passes.utils import ModuleGraph, to_flow, flow, create_exps, get_info, has_flip
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from pyhcl.passes.wir import *
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# ScopeView
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class ScopeView:
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def __init__(self, moduleNS: set, scopes: List[set]):
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self.moduleNS = moduleNS
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self.scopes = scopes
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def declare(self, name: str):
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self.moduleNS.add(name)
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self.scopes[0].add(name)
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# ensures that the name cannot be used again, but prevent references to this name
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def add_to_namespace(self, name: str):
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self.moduleNS.add(name)
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def expand_m_port_visibility(self, port: DefMemPort):
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mem_in_scopes = False
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def expand_m_port(scope: set, mp: DefMemPort):
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if mp.mem.name in scope:
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scope.add(mp.name)
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return scope
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self.scopes = list(map(lambda scope: expand_m_port(scope, port), self.scopes))
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for sx in self.scopes:
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if port.mem.name in sx:
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mem_in_scopes = True
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if mem_in_scopes is False:
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self.scopes[0].add(port.name)
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def legal_decl(self, name: str) -> bool:
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return name in self.moduleNS
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def legal_ref(self, name: str) -> bool:
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for s in self.scopes:
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if name in s:
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return True
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return False
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def get_ref(self):
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for s in self.scopes:
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print(s)
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def child_scope(self):
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return ScopeView(self.moduleNS, [set()])
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def scope_view():
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return ScopeView(set(), [set()])
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# Custom Exceptions
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class NotUniqueException(PassException):
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def __init__(self, info: Info, mname: str, name: str):
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super().__init__(f'{info}: [module {mname}] Reference {name} does not have a unique name.')
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class InvalidLOCException(PassException):
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def __init__(self, info: Info, mname: str):
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super().__init__(f'{info}: [module {mname}] Invalid connect to an expression that is not a reference or a WritePort.')
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class NegUIntException(PassException):
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def __init__(self, info: Info, mname: str):
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super().__init__(f'{info}: [module {mname}] UIntLiteral cannot be negative.')
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class UndecleardReferenceException(PassException):
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def __init__(self, info: Info, mname: str, name: str):
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super().__init__(f'{info}: [module {mname}] Reference {name} is not declared.')
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class PoisonWithFlipException(PassException):
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def __init__(self, info: Info, mname: str, name: str):
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super().__init__(f'{info}: [module {mname}] Poison {name} cannot be a bundle type with flips.')
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class MemWithFlipException(PassException):
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def __init__(self, info: Info, mname: str, name: str):
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super().__init__(f'{info}: [module {mname}] Memory {name} cannot be a bundle type with flips.')
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class IllegalMemLatencyException(PassException):
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def __init__(self, info: Info, mname: str, name: str):
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super().__init__(f'{info}: [module {mname}] Memory {name} must have non-negative read latency and positive write latency.')
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class RegWithFlipException(PassException):
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def __init__(self, info: Info, mname: str, name: str):
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super().__init__(f'{info}: [module {mname}] Register {name} cannot be a bundle type with flips.')
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class InvalidAccessException(PassException):
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def __init__(self, info: Info, mname: str):
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super().__init__(f'{info}: [module {mname}] Invalid access to non-reference.')
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class ModuleNameNotUniqueException(PassException):
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def __init__(self, info: Info, mname: str):
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super().__init__(f'{info}: Repeat definition of module {mname}')
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class DefnameConflictException(PassException):
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def __init__(self, info: Info, mname: str, defname: str):
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super().__init__(f'{info}: defname {defname} of extmodule {mname} conflicts with an existing module.')
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class DefnameDifferentPortsException(PassException):
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def __init__(self, info: Info, mname: str, defname: str):
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super().__init__(f'{info}: ports of extmodule {mname} with defname {defname} are different for an extmodule with the same defname.')
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class DefnameDifferentPortsException(PassException):
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def __init__(self, info: Info, name: str):
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super().__init__(f'{info}: Module {name} is not defined.')
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class IncorrectNumArgsException(PassException):
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def __init__(self, info: Info, mname: str, op: str, n: int):
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super().__init__(f'{info}: [module {mname}] Primop {op} requires {n} expression arguments.')
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class IncorrectNumConstsException(PassException):
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def __init__(self, info: Info, mname: str, op: str, n: int):
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super().__init__(f'{info}: [module {mname}] Primop {op} requires {n} integer arguments.')
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class NegWidthException(PassException):
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def __init__(self, info: Info, mname: str):
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super().__init__(f'{info}: [module {mname}] Width cannot be negative.')
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class NegVecSizeException(PassException):
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def __init__(self, info: Info, mname: str):
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super().__init__(f'{info}: [module {mname}] Vector type size cannot be negative.')
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class NegMemSizeException(PassException):
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def __init__(self, info: Info, mname: str):
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super().__init__(f'{info}: [module {mname}] Memory size cannot be negative or zero.')
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class InstanceLoop(PassException):
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def __init__(self, info: Info, mname: str, loop: str):
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super().__init__(f'{info}: [module {mname}] Has instance loop {loop}.')
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class NoTopModuleException(PassException):
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def __init__(self, info: Info, name: str):
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super().__init__(f'{info}: A single module must be named {name}.')
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class NegArgException(PassException):
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def __init__(self, info: Info, mname: str, op: str, value: int):
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super().__init__(f'{info}: [module {mname}] Primop {op} argument {value} < 0.')
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class LsbLargerThanMsbException(PassException):
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def __init__(self, info: Info, mname: str, op: str, lsb: int, msb: int):
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super().__init__(f'{info}: [module {mname}] Primop {op} lsb {lsb} > {msb}.')
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class ResetInputException(PassException):
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def __init__(self, info: Info, mname: str, expr: Expression):
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super().__init__(f'{info}: [module {mname}] Abstract Reset not allowed as top-level input: {expr.serialize()}')
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class ResetExtModuleOutputException(PassException):
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def __init__(self, info: Info, mname: str, expr: Expression):
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super().__init__(f'{info}: [module {mname}] Abstract Reset not allowed as ExtModule output: {expr.serialize()}')
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class ModuleNotDefinedException(PassException):
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def __init__(self, info: Info, mname: str, name: str):
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super().__init__(f'{info}: Module {name} is not defined.')
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class CircuitHasNoModules(PassException):
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def __init__(self, info: Info, cname: str):
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super().__init__(f'{info}: Circuit {cname} has no modules.')
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class ModuleHasNoPorts(PassException):
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def __init__(self, info: Info, mname: str):
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super().__init__(f'{info}: Module {mname} has no ports.')
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class ModuleHasNoBody(PassException):
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def __init__(self, info: Info, mname: str):
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super().__init__(f'{info}: Module {mname} has no body.')
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class CheckHighForm(Pass):
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def __init__(self, c: Circuit):
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self.c: Circuit = c
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self.ms: List[DefModule] = c.modules
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self.module_names: List[str] = [_.name for _ in c.modules]
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self.int_module_name: List[str] = [_.name for _ in c.modules if isinstance(_, Module)]
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self.errors: Error = Error()
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def check_unique_module_name(self):
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for idx in range(len(self.module_names)):
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if self.int_module_name[idx] in self.int_module_name[idx:]:
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m = self.ms[idx]
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self.errors.append(ModuleNameNotUniqueException(m.info, m.name))
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def check_extmodule(self):
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for m in self.ms:
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if isinstance(m, ExtModule) and m.name in self.int_module_name:
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self.errors.append(DefnameConflictException(m.info, m.name, m.defname))
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def strip_width(self, typ: Type) -> Type:
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if isinstance(typ, GroundType):
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return typ.map_width(UnknownWidth)
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elif isinstance(typ, AggregateType):
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return typ.map_type(self.strip_width())
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def check_highForm_primOp(self, info: Info, mname: str, e: DoPrim):
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def correct_num(ne, nc):
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if isinstance(ne, int) and len(e.args) != ne:
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self.errors.append(IncorrectNumArgsException(info, mname, e.op.serialize(), ne))
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if len(e.consts) != nc:
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self.errors.append(IncorrectNumConstsException(info, mname, e.op.serialize(), nc))
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def non_negative_consts():
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for _ in [c for c in e.consts if c < 0]:
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self.errors.append(NegArgException(info, mname, e.op.serialize(), _))
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if isinstance(e.op, (Add, Sub, Mul, Div, Rem, Lt, Leq, Gt, Geq, Eq, Neq, Dshl, Dshr, And, Or, Xor, Cat)):
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correct_num(2, 0)
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elif isinstance(e.op, (AsUInt, AsSInt, AsClock, Cvt, Neq, Not)):
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correct_num(1, 0)
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elif isinstance(e.op, AsFixedPoint):
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correct_num(1, 1)
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elif isinstance(e.op, (Shl, Shr, Pad, Head, Tail)):
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correct_num(1, 1)
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non_negative_consts()
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elif isinstance(e.op, Bits):
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correct_num(1, 2)
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non_negative_consts()
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if len(e.consts) == 2:
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msb, lsb = e.consts[0], e.consts[1]
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if msb < lsb:
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self.errors.append(LsbLargerThanMsbException(info, mname, e.op.serialize(), lsb, msb))
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elif isinstance(e.op, (Andr, Orr, Xorr, Neg)):
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correct_num(1, 0)
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def check_valid_loc(self, info: Info, mname: str, e: Expression):
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if isinstance(e, (UIntLiteral, SIntLiteral, DoPrim)):
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self.errors.append(InvalidLOCException(info, mname))
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def check_instance(self, info: Info, child: str, parent: str):
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if child not in self.module_names:
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self.errors.append(ModuleNotDefinedException(info, parent, child))
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childToParent = ModuleGraph().add(parent, child)
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if childToParent is not None and len(childToParent) > 0:
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self.errors.append(InstanceLoop(info, parent, "->".join(childToParent)))
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def check_high_form_w(self, info: Info, mname: str, w: Width):
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if isinstance(w, IntWidth) and w.width < 0:
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self.errors.append(NegWidthException(info, mname))
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def check_high_form_t(self, info: Info, mname: str, typ: Type):
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t_attr = typ.__dict__.items()
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for _, ta in t_attr:
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if isinstance(ta, Type):
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self.check_high_form_t(info, mname, ta)
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if isinstance(ta, Width):
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self.check_high_form_w(info, mname, ta)
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if isinstance(typ, VectorType) and typ.size < 0:
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self.errors.append(NegVecSizeException(info, mname))
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def valid_sub_exp(self, info: Info, mname: str, e: Expression):
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if isinstance(e, (Reference, SubField, SubIndex, SubAccess)):
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...
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elif isinstance(e, (Mux, ValidIf)):
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...
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else:
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self.errors.append(InvalidAccessException(info, mname))
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def check_high_form_e(self, info: Info, mname: str, names: ScopeView, e: Expression):
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e_attr = e.__dict__.items()
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if isinstance(e, Reference) and names.legal_ref(e.name) is False:
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self.errors.append(UndecleardReferenceException(info, mname, e.name))
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...
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elif isinstance(e, UIntLiteral) and e.value < 0:
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self.errors.append(NegUIntException(info, mname, e.name))
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elif isinstance(e, DoPrim):
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self.check_highForm_primOp(info, mname, e)
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elif isinstance(e, (Reference, UIntLiteral, Mux, ValidIf)):
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...
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elif isinstance(e, SubAccess):
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self.valid_sub_exp(info, mname, e.expr)
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else:
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for _, ea in e_attr:
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if isinstance(ea, Expression):
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self.valid_sub_exp(info, mname, ea)
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for _, ea in e_attr:
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if isinstance(ea, Width):
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self.check_high_form_w(info, mname + '/' + e.serialize(), ea)
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if isinstance(ea, Expression):
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self.check_high_form_e(info, mname, names, ea)
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def check_name(self, info: Info, mname: str, names: ScopeView, referenced: bool, s: Statement):
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if referenced is False:
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return
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if len(s.name) == 0:
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assert referenced is False, 'A statement with an empty name cannot be used as a reference!'
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else:
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if names.legal_decl(s.name) is True:
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self.errors.append(NotUniqueException(info, mname, s.name))
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if referenced:
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names.declare(s.name)
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else:
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names.add_to_namespace(s.name)
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def check_high_form_s(self, minfo: Info, mname: str, names: ScopeView, s: Statement):
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s_attr = s.__dict__.items()
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t_info = get_info(s)
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info = t_info if isinstance(t_info, NoInfo) is False else minfo
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referenced = True if isinstance(s, (DefWire, DefRegister, DefInstance, DefMemory, DefNode, Port)) else False
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self.check_name(info, mname, names, referenced, s)
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if isinstance(s, DefRegister):
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if has_flip(s.typ):
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self.errors.append(RegWithFlipException(info, mname, s.name))
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elif isinstance(s, DefMemory):
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if has_flip(s.memType.typ):
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self.errors.append(MemWithFlipException(info, mname, s.name))
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if s.memType.size < 0:
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self.errors.append(NegMemSizeException(info, mname))
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elif isinstance(s, DefInstance):
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self.check_instance(info, mname, s.module)
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elif isinstance(s, Connect):
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self.check_valid_loc(info, mname, s.loc)
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elif isinstance(s, DefMemPort):
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names.expand_m_port_visibility(s)
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elif isinstance(s, Block):
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for stmt in s.stmts:
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self.check_high_form_s(info, mname, names, stmt)
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else:
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...
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for _, sa in s_attr:
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if isinstance(sa, Type):
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self.check_high_form_t(info, mname, sa)
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elif isinstance(sa, Expression):
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self.check_high_form_e(info, mname, names, sa)
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if isinstance(s, Conditionally):
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self.check_high_form_s(minfo, mname, names, s.conseq)
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self.check_high_form_s(minfo, mname, names, s.alt)
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else:
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for _, sa in s_attr:
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if isinstance(sa, Statement):
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self.check_high_form_s(minfo, mname, names, sa)
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def check_high_form_p(self, mname: str, names: ScopeView, p: Port):
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if names.legal_decl(p.name) is True:
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self.errors.append(NotUniqueException(NoInfo, mname, p.name))
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names.declare(p.name)
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self.check_high_form_t(p.info, mname, p.typ)
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def find_bad_reset_type_ports(self, m: DefModule, dir: Direction):
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bad_reset_type_ports = []
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bad = to_flow(dir)
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gen = ((create_exps(ref), p1) for (ref, p1) in [(Reference(p.name, p.typ), p) for p in m.ports])
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for expr, port in gen:
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if isinstance(expr, list):
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for exx in expr:
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if exx is not None and exx.typ == ResetType and flow(exx) == bad:
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bad_reset_type_ports.append((port, exx))
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else:
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if expr is not None and expr.typ == ResetType and flow(expr) == bad:
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bad_reset_type_ports.append((port, expr))
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return bad_reset_type_ports
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def check_high_form_m(self, m: DefModule):
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names = scope_view()
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if hasattr(m, 'ports') and isinstance(m.ports, list):
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for p in m.ports:
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self.check_high_form_p(m.name, names, p)
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else:
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self.errors.append(ModuleHasNoPorts(m.info, m.name))
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if hasattr(m, 'body') and isinstance(m.body, Block):
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if hasattr(m.body, 'stmts') and isinstance(m.body.stmts, list):
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for s in m.body.stmts:
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self.check_high_form_s(m.info, m.name, names, s)
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else:
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self.errors.append(ModuleHasNoBody(m.info, m.name))
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if isinstance(m, ExtModule):
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for port, expr in self.find_bad_reset_type_ports(m, Output):
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self.errors.append(ResetExtModuleOutputException(port.info, m.name, expr))
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def run(self):
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if hasattr(self.c, 'modules') and isinstance(self.c.modules, list):
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for m in self.c.modules:
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self.check_high_form_m(m)
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else:
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self.errors.append(CircuitHasNoModules(self.c.info, self.c.main))
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if self.c.main not in self.int_module_name:
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self.errors.append(NoTopModuleException(self.c.info, self.c.main))
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self.errors.trigger()
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return self.c
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