forked from opendacs/PyHCL
139 lines
4.8 KiB
Python
139 lines
4.8 KiB
Python
# Copyright (c) 2019 scutdig
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# Licensed under the MIT license.
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from collections import deque
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from typing import Optional, Dict, Counter
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from pyhcl.core._dynamic_ctx import DynamicContext
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from pyhcl.ir import low_ir
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class EmitterContext:
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def __init__(self, module: "Module",
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emittedModules: Dict[int, low_ir.DefModule],
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moduleNameCounter: Counter):
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# generate the name
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modClass = module.__class__
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self._modClass = modClass
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modName = modClass.__name__
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c = moduleNameCounter[modName]
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moduleNameCounter[modName] += 1
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self.name = modName + (("_" + str(c)) if c > 0 else "") # dup
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# bunch of records
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self._module = module
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self._rawStatements = deque(modClass._statements)
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self._rawNameTable = modClass._rawTable
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self._emittedModules: Dict[int, low_ir.DefModule] = emittedModules
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self._moduleNameCounter = moduleNameCounter
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self._innerRef = {}
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self._finalStatements = {}
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self._finalPorts = []
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self._nameIndex = -1
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def prependRawStatement(self, statement):
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self._rawStatements.appendleft(statement)
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def appendFinalStatement(self, statement, scopeId):
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if self._finalStatements.get(scopeId) is None:
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self._finalStatements[scopeId] = []
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self._finalStatements[scopeId].append(statement)
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def getScopeStatements(self, scopeId):
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return self._finalStatements[scopeId] if scopeId in self._finalStatements else None
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def appendFinalPort(self, port):
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self._finalPorts.append(port)
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def updateRef(self, obj, ref):
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self._innerRef[id(obj)] = ref
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def getRef(self, obj) -> Optional:
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from pyhcl.core._meta_pub import Pub
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if isinstance(obj, Pub):
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obj = obj.value
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r = self._innerRef.get(id(obj))
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if r is not None:
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return r
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else:
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ref = obj.mapToIR(self)
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return ref
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def emit(self) -> Dict[int, low_ir.DefModule]:
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self._dealWithClockAndReset()
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scopeId = DynamicContext.currentScope()
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while len(self._rawStatements) > 0:
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lf = self._rawStatements.popleft()
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lf.mapToIR(self)
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self._dealWithVerifaction()
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modBundle = self._mapToBundle(self._finalPorts)
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finalMod = low_ir.Module(self.name,
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self._finalPorts,
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low_ir.Block(self.getScopeStatements(scopeId)),
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modBundle)
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self._emittedModules[id(self._modClass)] = finalMod
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return self._emittedModules
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'''
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This Function is to deal with clock and reset, composed of default and user-defined clk and rst.
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user-defined clk and rst are not allowed to use the name of "clock" or "reset".
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It's stupid and ugly but ... I will fix it if there is a better idea.
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'''
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def _dealWithClockAndReset(self):
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if not self._modClass.raw:
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c = self._modClass.clock.public()
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r = self._modClass.reset.public()
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c.mapToIR(self)
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r.mapToIR(self)
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self._finalStatements[c.scopeId] = []
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from pyhcl.core._meta_pub import Pub
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for k, v in self._modClass.__dict__.items():
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if type(v) == Pub and k != "io" and k != "clock" and k != "reset":
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v.mapToIR(self)
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def _dealWithVerifaction(self):
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from pyhcl.dsl.verifaction import _Verfication
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for k, v in self._modClass.__dict__.items():
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if(isinstance(v,_Verfication)):
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v.mapToIR(self)
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def getName(self, obj):
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res = self._rawNameTable.get(id(obj))
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if res is not None:
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return res
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else:
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self._nameIndex += 1
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return "_T" + (("_" + str(self._nameIndex)) if self._nameIndex > 0 else "")
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def extendNewEnv(self, module):
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return EmitterContext(module, self._emittedModules, self._moduleNameCounter)
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def _mapToBundle(self, finalPorts):
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fs = []
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for i in finalPorts:
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if i.direction == low_ir.Input():
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fs.append(low_ir.Field(i.name, low_ir.Flip(), i.typ))
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else:
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fs.append(low_ir.Field(i.name, low_ir.Default(), i.typ))
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return low_ir.BundleType(fs)
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def getClock(self, m):
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from pyhcl.core._clock_manager import Clock_manager
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clock_obj = Clock_manager.getClockByID(id(m))
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return low_ir.Reference(self.getName(clock_obj.extractForName()), low_ir.UIntType(low_ir.IntWidth(1)))
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def getReset(self, m):
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from pyhcl.core._clock_manager import Clock_manager
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reset_obj = Clock_manager.getResetByID(id(m))
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return low_ir.Reference(self.getName(reset_obj.extractForName()), low_ir.UIntType(low_ir.IntWidth(1)))
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