forked from opendacs/PyHCL
20 lines
371 B
Plaintext
20 lines
371 B
Plaintext
circuit M :
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module Add :
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input in1 : UInt<32>
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input in2 : UInt<32>
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output out : UInt<32>
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out <= add(in1, in2)
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module M :
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input clock : Clock
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input reset : UInt<1>
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output io : {flip a : UInt<32>, flip b : UInt<32>, c : UInt<32>}
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inst bbox of Add
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bbox.in1 <= io.a
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bbox.in2 <= io.b
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io.c <= bbox.out
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