forked from opendacs/PyHCL
24 lines
332 B
Systemverilog
24 lines
332 B
Systemverilog
// Pysv
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module Add(
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input [31:0] in1 ,
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input [31:0] in2 ,
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output [31:0] out
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);
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wire [31:0] __tmp_in1 ;
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wire [31:0] __tmp_in2 ;
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reg [31:0] __tmp_out ;
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assign __tmp_in1 = in1 ;
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assign __tmp_in2 = in2 ;
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import pysv::* ;
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always begin
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fn(__tmp_in1, __tmp_in2, __tmp_out) ;
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end
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assign out = __tmp_out ;
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endmodule
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