forked from opendacs/PyHCL
21 lines
340 B
Verilog
21 lines
340 B
Verilog
module Top(
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input clock,
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input reset,
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input [31:0] io_a,
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input [31:0] io_b,
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output [31:0] io_c
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);
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wire [31:0] add_in1;
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wire [31:0] add_in2;
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wire [31:0] add_out;
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Add add (
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.in1(add_in1),
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.in2(add_in2),
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.out(add_out)
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);
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assign io_c = add_out;
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assign add_in1 = io_a;
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assign add_in2 = io_b;
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endmodule
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