forked from opendacs/PyHCL
80 lines
2.0 KiB
Python
80 lines
2.0 KiB
Python
# Copyright (c) 2019 scutdig
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# Licensed under the MIT license.
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from pyhcl.util.pysvtools import compile_and_binding_all_func
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from pyhcl.simulator.simlite_verilog import Simlite, DpiConfig
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from pysv import sv, DataType, Reference
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import random
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@sv(a=DataType.UInt, b=DataType.UInt, return_type=Reference(x=DataType.UInt))
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def fn(a, b):
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return a + b
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# 传入函数列表
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# 编译得到共享库 到.build文件夹下, 生成 SV binding文件 （.sv/pkg/pysv_pkg.sv）
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compile_and_binding_all_func([fn])
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# 每次给输入端口赋值, 跑一个时间单位
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def test_step(s):
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s.start()
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s.step([0, 0, 20, 20])
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print("cnt: %d\t\tresult:%s" % (s.cnt, s.getRes()))
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s.step([1, 0, 15, 10])
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print("cnt: %d\t\tresult:%s" % (s.cnt, s.getRes()))
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s.step([0, 0, 1000, 1])
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print("cnt: %d\t\tresult:%s" % (s.cnt, s.getRes()))
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s.step([1, 0, 999, 201])
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print("cnt: %d\t\tresult:%s" % (s.cnt, s.getRes()))
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s.stop()
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def test_task(s):
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tasks = []
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tasks.append([0, 0, 20, 20])
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tasks.append([1, 0, 15, 10])
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tasks.append([0, 0, 1000, 1])
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tasks.append([1, 0, 999, 201])
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s.start_task('Top', tasks)
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def randomInput(ifn):
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fd = open(ifn, "w")
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instr = ""
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for i in range(100):
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instr += "0 0 0 " + str(random.randint(1, 2000)) + ' ' + str(random.randint(1, 2000)) + "\n"
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instr = instr + "-1\n"
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fd.write(instr)
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fd.close()
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def test_file(s):
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ifn = f"../myTests/tmp/Top_inputs"
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ofn = f"../myTests/tmp/Top_outputs"
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randomInput(ifn)
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s.start(mode="task", ofn=ofn, ifn=ifn)
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pass
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def main():
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# Emitter.dumpVerilog(Emitter.dump(Emitter.emit(Top()), "Add.fir"))
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top_module_name = 'Top.v'
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dut_path = 'myTests/tmp/dut_pysv/'
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# 创建 DpiConfig对象，传入调用Python函数的SV文件名列表
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cfg = DpiConfig(['Add.sv'])
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s = Simlite(top_module_name, dut_path, dpiconfig=cfg, debug=True)
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# test_step(s)
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# test_task(s)
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test_file(s)
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s.close()
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if __name__ == '__main__':
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main()
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