forked from opendacs/PyHCL
111 lines
3.6 KiB
Python
111 lines
3.6 KiB
Python
# Copyright (c) 2019 scutdig
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# Licensed under the MIT license.
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from typing import Type, Union, Dict
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class IO:
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_ios: Dict[str, int]
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def __init__(self, **kwargs):
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self._ios = kwargs
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class Add:
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io = IO(
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in1=3,
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in2=4,
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out=5
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)
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import re
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# 解析FIRRTL代码, 返回输入端口名列表 和 输出端口名列表
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def firrtl_parse(firrtl_path):
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circuit_begin_match = r"circuit\s*([a-zA-Z0-9_]+)"
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module_begin_match = r"module\s*([a-zA-Z0-9_]+)"
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input_port_match = r"input\s*([a-zA-Z0-9_]+)"
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output_port_match = r"output\s*([a-zA-Z0-9_]+)"
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input_ports_name = []
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output_ports_name = []
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top_module_name = '0'
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current_module_name = '1'
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with open(firrtl_path, "r") as firrtl_file:
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while firrtl_file:
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firrtl_line = firrtl_file.readline().strip(' ') # 读取一行
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# print(firrtl_line)
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if firrtl_line == "": # 注：如果是空行，为'\n'
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break
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circuit_begin = re.search(circuit_begin_match, firrtl_line)
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module_begin = re.search(module_begin_match, firrtl_line)
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if circuit_begin:
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top_module_name = circuit_begin.group(1)
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# print(top_module_name)
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if module_begin:
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current_module_name = module_begin.group(1)
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# print(current_module_name)
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if current_module_name == top_module_name:
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input_port = re.search(input_port_match, firrtl_line)
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output_port = re.search(output_port_match, firrtl_line)
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if input_port:
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input_ports_name.append(input_port.group(1))
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if output_port:
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output_ports_name.append(output_port.group(1))
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print(top_module_name)
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print(input_ports_name)
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print(output_ports_name)
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return top_module_name, input_ports_name, output_ports_name
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# 解析verilog代码, 返回输入端口名列表 和 输出端口名列表
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def verilog_parse(dut_path, top_module_name):
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dut_name = top_module_name.split('.')[0] # 模块名
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top_module_path = dut_path + top_module_name
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# print(top_module_path)
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module_begin_match = r"module\s*([a-zA-Z0-9_]+)"
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input_port_match = r"input\s*(reg|wire)*\s*(\[[0-9]+\:[0-9]+\]*)*\s*([a-zA-Z0-9_]+)"
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output_port_match = r"output\s*(reg|wire)*\s*(\[[0-9]+\:[0-9]+\]*)*\s*([a-zA-Z0-9_]+)"
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input_ports_name = []
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output_ports_name = []
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with open(top_module_path, "r") as verilog_file:
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while verilog_file:
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verilog_line = verilog_file.readline().strip(' ') # 读取一行
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# print(verilog_line)
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if verilog_line == "": # 注：如果是空行，为'\n'
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break
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module_begin = re.search(module_begin_match, verilog_line)
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if module_begin:
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current_module_name = module_begin.group(1)
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# print(current_module_name)
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if current_module_name == dut_name:
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input_port = re.search(input_port_match, verilog_line)
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output_port = re.search(output_port_match, verilog_line)
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if input_port:
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input_ports_name.append(input_port.group(3))
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if output_port:
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output_ports_name.append(output_port.group(3))
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# print(dut_name)
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# print(input_ports_name)
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# print(output_ports_name)
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return input_ports_name, output_ports_name
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if __name__ == '__main__':
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# verilog_parse('./tmp/dut/', 'Top.v')
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verilog_parse('../simulation/', 'M.v')
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# firrtl_parse('./tmp/firrtl/M.fir')
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