forked from opendacs/PyHCL
29 lines
706 B
Python
29 lines
706 B
Python
# Copyright (c) 2019 scutdig
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# Licensed under the MIT license.
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from pyhcl import *
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class FullAdder(Module):
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io = IO(
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a=Input(Bool),
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b=Input(Bool),
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cin=Input(Bool),
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sum=Output(Bool),
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cout=Output(Bool),
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)
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# Generate the sum
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io.sum @= io.a ^ io.b ^ io.cin
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# Generate the carry
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io.cout @= io.a & io.b | io.b & io.cin | io.a & io.cin
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if __name__ == '__main__':
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# emit high firrtl
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Emitter.dump(Emitter.emit(FullAdder(), HighForm), "FullAdder.fir")
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# emit lowered firrtl
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Emitter.dump(Emitter.emit(FullAdder(), LowForm), "FullAdder.lo.fir")
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# emit verilog
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Emitter.dump(Emitter.emit(FullAdder(), Verilog), "FullAdder.v")
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