forked from opendacs/PyHCL
239 lines
7.0 KiB
Python
239 lines
7.0 KiB
Python
# Copyright (c) 2019 scutdig
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# Licensed under the MIT license.
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# from pyhcl import *
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# from pysv import sv, DataType, Reference
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# from pyhcl.simulator import Simlite, DpiConfig
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from queue import Queue
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import asyncio
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from injector.reader import read_wave
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# class Add(BlackBox):
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# io = IO(
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# in1=Input(U.w(32)),
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# in2=Input(U.w(32)),
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# out=Output(U.w(32))
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# )
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#
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#
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# @sv(a=DataType.UInt, b=DataType.UInt, return_type=Reference(x=DataType.UInt))
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# def fn(a, b):
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# return a + b
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#
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#
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# addpysvmodule(Add, fn) # 黑盒与函数 # 转换得到.sv/bbox/Add.sv，（SV里调用python函数）
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# compile_and_binding_all() # 编译得到共享库 到.build文件夹下, 生成 SV binding文件 （.sv/pkg/pysv_pkg.sv）
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#
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#
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# class Top(Module):
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# io = IO(
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# a=Input(U.w(32)),
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# b=Input(U.w(32)),
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# c=Output(U.w(32))
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# )
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#
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# add = Add()
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# add.io.in1 @= io.a
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# add.io.in2 @= io.b
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# io.c @= add.io.out
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from random import randint
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class in_intf:
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def __init__(self):
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self.input_data = []
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class out_intf:
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def __init__(self):
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self.output_data = []
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# class driver:
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# def __init__(self, name, s: Simlite, time_period):
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# self.name = name
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# self.req_mb = Queue()
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# self.simlite = s
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# self.time_period = time_period
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#
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# async def run(self):
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# for i in range(3):
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# input_data = [15 + i, 10 + i]
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# self.simlite.step(input_data)
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# print("%s drivered data %s" % (self.name, input_data))
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# await asyncio.sleep(self.time_period)
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#
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# def set_interface(self, intf):
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# self.intf = intf
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class in_monitor:
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def __init__(self, name, time_period):
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self.name = name
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self.input_mb = Queue()
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self.time_period = time_period
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self.input_data = 0
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async def run(self):
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await asyncio.sleep(self.time_period/2)
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while True:
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if self.intf.input_data != self.input_data:
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self.input_data = self.intf.input_data
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print("%s monitored input data %s" % (self.name, self.input_data))
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self.input_mb.put(self.input_data)
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await asyncio.sleep(self.time_period)
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def set_interface(self, intf):
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self.intf = intf
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class out_monitor:
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def __init__(self, name, time_period):
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self.name = name
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self.output_mb = Queue()
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self.time_period = time_period
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self.output_data = 0
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async def run(self):
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await asyncio.sleep(self.time_period/2)
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while True:
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if self.intf.output_data != self.output_data:
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self.output_data = self.intf.output_data
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print("%s monitored output data %s" % (self.name, self.output_data))
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self.output_mb.put(self.output_data)
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await asyncio.sleep(self.time_period)
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def set_interface(self, intf):
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self.intf = intf
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class checker:
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def __init__(self, name, time_period):
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self.name = name
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self.error_count = 0
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self.cmp_count = 0
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self.in_mb = Queue()
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self.out_mb = Queue()
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self.time_period = time_period
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async def run(self):
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await self.do_compare()
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async def do_compare(self):
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while True:
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while self.out_mb.empty() or self.in_mb.empty():
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await asyncio.sleep(self.time_period)
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outputs = self.out_mb.get()
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inputs = self.in_mb.get()
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# print(inputs, outputs)
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result = sum(inputs)
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if result == outputs[0]:
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print("succeed:output data %d is equal with desired data %d" % (outputs[0], result))
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else:
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print("failed:output data %d is not equal with desired data %d" % (outputs[0], result))
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self.cmp_count = self.cmp_count + 1
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# await asyncio.sleep(self.time_period)
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async def inject_values(time_period, in_intf, out_intf, wavefile):
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data = waveRead(wavefile)
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sim_time = 0
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while True:
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print()
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# values为字典{'信号':'值',...}--存放仿真时刻sim_time时各信号量的值
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values = data.get_values_at(sim_time)
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# print(values)
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# 注入当前仿真时刻的信号与值
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# injector.inject_values(values)
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input_data = [values['TOP.io_a'], values['TOP.io_b']]
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input_data = [int(k, base=2) for k in input_data]
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output_data = [values['TOP.io_c']]
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output_data = [int(k, base=2) for k in output_data]
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in_intf.input_data = input_data
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out_intf.output_data = output_data
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print("inject input_data %s and output_data %s" % (input_data, output_data))
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await asyncio.sleep(time_period)
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previous_time = sim_time
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# 得到仿真时刻sim_time后的一个变化时刻，若无则返回None
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sim_time = data.get_next_event(sim_time)
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if sim_time is None:
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break
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# await Timer(sim_time - previous_time)
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# for i in range(3):
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# input_data = [15 + i, 10 + i]
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# output_data = [sum(input_data)]
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# in_intf.input_data = input_data
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# out_intf.output_data = output_data
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# print("inject input_data %s and output_data %s" % (input_data, output_data))
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# await asyncio.sleep(time_period)
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pass
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def waveRead(wavefile):
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replay_block = []
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excluded_sigs = []
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inputs_only = False
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data = read_wave(wavefile, replay_block, inputs_only, excluded_sigs) # VcdReader对象
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print(data.signal_values)
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return data
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async def func(time_period):
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# driver1 = driver("driver", s, time_period)
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i_monitor = in_monitor("in_monitor", time_period)
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o_monitor = out_monitor("out_monitor", time_period)
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checker1 = checker("checker", time_period)
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i_monitor.input_mb = checker1.in_mb
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o_monitor.output_mb = checker1.out_mb
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i_intf = in_intf()
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o_intf = out_intf()
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i_monitor.set_interface(i_intf)
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o_monitor.set_interface(o_intf)
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# driver_task = asyncio.create_task(driver1.run())
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i_monitor_task = asyncio.create_task(i_monitor.run())
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o_monitor_task = asyncio.create_task(o_monitor.run())
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checker_task = asyncio.create_task(checker1.run())
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# await driver_task
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# await monitor_task
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wavefile = "simulation/wave.vcd"
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inject_task = asyncio.create_task(inject_values(time_period, i_intf, o_intf, wavefile))
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await inject_task
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await asyncio.sleep(1)
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def main():
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# cfg = DpiConfig()
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# Emitter.dumpVerilog(Emitter.dump(Emitter.emit(Top()), "Top.fir"))
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# s = Simlite(Top(), dpiconfig=cfg, debug=True)
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# s.start()
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time_period = 0.1
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asyncio.run(func(time_period))
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# s.close()
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if __name__ == '__main__':
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# cfg = DpiConfig()
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# # Emitter.dumpVerilog(Emitter.dump(Emitter.emit(Top()), "Top.fir"))
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# s = Simlite(Top(), dpiconfig=cfg, debug=True)
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# s.start()
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# s.step([20, 20])
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# s.step([15, 10])
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# s.step([1000, 1])
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# s.step([999, 201])
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# s.close()
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# wavefile = "../simulation/wave.vcd"
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# waveRead(wavefile)
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main() |