forked from opendacs/PyHCL
147 lines
4.1 KiB
Python
147 lines
4.1 KiB
Python
# Copyright (c) 2019 scutdig
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# Licensed under the MIT license.
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from pyhcl import *
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from pysv import sv, DataType, Reference
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from pyhcl.simulator import Simlite, DpiConfig
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from queue import Queue
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import asyncio
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class Add(BlackBox):
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io = IO(
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in1=Input(U.w(32)),
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in2=Input(U.w(32)),
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out=Output(U.w(32))
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)
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@sv(a=DataType.UInt, b=DataType.UInt, return_type=Reference(x=DataType.UInt))
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def fn(a, b):
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return a + b
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addpysvmodule(Add, fn) # 黑盒与函数 # 转换得到.sv/bbox/Add.sv，（SV里调用python函数）
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compile_and_binding_all() # 编译得到共享库 到.build文件夹下, 生成 SV binding文件 （.sv/pkg/pysv_pkg.sv）
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class Top(Module):
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io = IO(
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a=Input(U.w(32)),
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b=Input(U.w(32)),
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c=Output(U.w(32))
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)
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add = Add()
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add.io.in1 @= io.a
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add.io.in2 @= io.b
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io.c @= add.io.out
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from random import randint
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class driver:
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def __init__(self, name, s: Simlite, time_period):
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self.name = name
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self.req_mb = Queue()
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self.simlite = s
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self.time_period = time_period
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async def run(self):
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for i in range(3):
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input_data = [15 + i, 10 + i]
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self.simlite.step(input_data)
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print("%s drivered data %s" % (self.name, input_data))
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await asyncio.sleep(self.time_period)
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class monitor:
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def __init__(self, name, s: Simlite, time_period):
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self.name = name
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self.input_mb = Queue()
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self.output_mb = Queue()
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self.simlite = s
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self.cnt = self.simlite.cnt
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self.time_period = time_period
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async def run(self):
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await asyncio.sleep(self.time_period/2)
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while True:
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if self.simlite.cnt == self.cnt + 1:
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self.cnt = self.simlite.cnt
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input_data = self.simlite.inputs_values
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output_data = self.simlite.results
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print("%s monitored input data %s" % (self.name, input_data))
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print("%s monitored output data %s" % (self.name, output_data))
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self.input_mb.put(input_data)
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self.output_mb.put(output_data)
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await asyncio.sleep(self.time_period)
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class checker:
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def __init__(self, name, time_period):
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self.name = name
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self.error_count = 0
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self.cmp_count = 0
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self.in_mb = Queue()
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self.out_mb = Queue()
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self.time_period = time_period
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async def run(self):
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await self.do_compare()
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async def do_compare(self):
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while True:
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while self.out_mb.empty() or self.in_mb.empty():
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await asyncio.sleep(self.time_period)
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outputs = self.out_mb.get()
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inputs = self.in_mb.get()
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# print(inputs, outputs)
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result = sum(inputs)
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if result == outputs[0]:
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print("succeed:output data %d is equal with desired data %d" % (outputs[0], result))
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else:
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print("failed:output data %d is not equal with desired data %d" % (outputs[0], result))
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self.cmp_count = self.cmp_count + 1
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# await asyncio.sleep(self.time_period)
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async def func(s, time_period):
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driver1 = driver("driver", s, time_period)
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monitor1 = monitor("monitor", s, time_period)
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checker1 = checker("checker", time_period)
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monitor1.input_mb = checker1.in_mb
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monitor1.output_mb = checker1.out_mb
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driver_task = asyncio.create_task(driver1.run())
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monitor_task = asyncio.create_task(monitor1.run())
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checker_task = asyncio.create_task(checker1.run())
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await driver_task
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# await monitor_task
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await asyncio.sleep(1)
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def main():
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cfg = DpiConfig()
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# Emitter.dumpVerilog(Emitter.dump(Emitter.emit(Top()), "Top.fir"))
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s = Simlite(Top(), dpiconfig=cfg, debug=True)
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s.start()
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time_period = 0.1
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asyncio.run(func(s, time_period))
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s.close()
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if __name__ == '__main__':
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cfg = DpiConfig()
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# Emitter.dumpVerilog(Emitter.dump(Emitter.emit(Top()), "Top.fir"))
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s = Simlite(Top(), dpiconfig=cfg, debug=True)
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s.start()
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s.step([20, 20])
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s.step([15, 10])
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s.step([1000, 1])
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s.step([999, 201])
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s.close()
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