forked from opendacs/PyHCL
59 lines
1.2 KiB
Python
59 lines
1.2 KiB
Python
# Copyright (c) 2019 scutdig
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# Licensed under the MIT license.
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from pyhcl import *
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from pysv import sv, DataType, Reference
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from pyhcl.simulator import Simlite, DpiConfig
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class Add(BlackBox):
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io = IO(
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in1=Input(U.w(32)),
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in2=Input(U.w(32)),
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out=Output(U.w(32))
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)
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@sv(a=DataType.UInt, b=DataType.UInt, return_type=Reference(x=DataType.UInt))
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def fn(a, b):
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return a + b
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addpysvmodule(Add, fn)
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compile_and_binding_all()
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class Top(Module):
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io = IO(
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a=Input(U.w(32)),
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b=Input(U.w(32)),
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c=Output(U.w(32))
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)
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add = Add()
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add.io.in1 @= io.a
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add.io.in2 @= io.b
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io.c @= add.io.out
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import time
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def test():
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cfg = DpiConfig()
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# Emitter.dumpVerilog(Emitter.dump(Emitter.emit(Top()), "Top.fir"))
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s = Simlite(Top(), dpiconfig=cfg, debug=True)
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time1 = time.time()
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inputs = [[2000, 230032]]*40
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for i in range(2):
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s.start_task(f"task_{i}", inputs)
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time2 = time.time()
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print("time = " + str(time2 - time1))
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s.start_task(f"task_3", inputs)
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time3 = time.time()
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print("time = " + str(time3 - time2))
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s.close()
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if __name__ == '__main__':
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test() |