forked from opendacs/PyHCL
73 lines
1.6 KiB
Python
73 lines
1.6 KiB
Python
# Copyright (c) 2019 scutdig
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# Licensed under the MIT license.
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from pyhcl import *
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class Mul1(Module):
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"""
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Four-by-four multiply using a look-up table.
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"""
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io = IO(
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x=Input(U.w(4)),
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y=Input(U.w(4)),
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z=Output(U.w(8)),
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)
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# --------------------------------
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# Calculate io.z = io.x * io.y by
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# building filling out muls
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# --------------------------------
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muls = [U.w(8)(i * j) for i in range(16) for j in range(16)]
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tbl = VecInit(muls)
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io.z <<= tbl[io.x << U(4) | io.y]
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class Mul2(Module):
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"""
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Four-by-four multiply using a look-up table.
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"""
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io = IO(
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x=Input(U.w(4)),
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y=Input(U.w(4)),
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z=Output(U.w(8)),
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)
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# --------------------------------
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# Calculate io.z = io.x * io.y by
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# building filling out tbl
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# --------------------------------
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tbl = VecInit(VecInit(U.w(8)(i * j) for i in range(16)) for j in range(16))
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io.z <<= tbl[io.x][io.y]
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class Mul3(Module):
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"""
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Four-by-four multiply using a look-up table.
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"""
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io = IO(
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x=Input(U.w(2)),
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y=Input(U.w(2)),
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z=Input(U.w(2)),
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o=Output(U.w(6)),
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)
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# --------------------------------
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# Calculate io.z = io.x * io.y by
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# building filling out tbl
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# --------------------------------
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tbl = VecInit(VecInit(VecInit(U.w(6)(i * j * k) for k in range(4)) for i in range(4)) for j in range(4))
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io.o <<= tbl[io.x][io.y][io.z]
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def main():
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f = Emitter.dump(Emitter.emit(Mul1()), "mul.fir")
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Emitter.dumpVerilog(f)
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if __name__ == '__main__':
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main()
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