forked from opendacs/PyHCL
36 lines
654 B
Python
36 lines
654 B
Python
# Copyright (c) 2019 scutdig
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# Licensed under the MIT license.
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from functools import reduce
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from pyhcl import *
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def maxN(n: int, w: int):
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def _max2(x: U, y: U):
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return Mux(x > y, x, y)
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class MaxN(Module):
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io = IO(
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ins=Input(Vec(n, U.w(w))),
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out=Output(U.w(w)),
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)
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io.out @= reduce(_max2, io.ins)
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# temp = io.ins[0]
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# for x in io.ins[1:]:
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# temp = Mux(temp > x, temp, x)
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# io.out @= temp
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return MaxN()
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def main():
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f = Emitter.dump(Emitter.emit(maxN(16, 32)), "maxN.fir")
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Emitter.dumpVerilog(f)
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if __name__ == '__main__':
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main()
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