forked from opendacs/PyHCL
39 lines
605 B
Python
39 lines
605 B
Python
# Copyright (c) 2019 scutdig
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# Licensed under the MIT license.
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from pyhcl import *
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class GCD(Module):
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io = IO(
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a=Input(U.w(32)),
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b=Input(U.w(32)),
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e=Input(Bool),
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z=Output(U.w(32)),
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v=Output(Bool),
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)
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x = Reg(U.w(32))
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y = Reg(U.w(32))
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with when(x > y):
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x @= x - y
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with otherwise():
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y @= y - x
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with when(io.e):
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x @= io.a
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y @= io.b
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io.z @= x
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io.v @= y == U(0)
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def main():
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f = Emitter.dump(Emitter.emit(GCD()), "gcd.fir")
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Emitter.dumpVerilog(f)
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if __name__ == '__main__':
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main()
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